參數(shù)資料
型號(hào): XRT75R03IVTR-F
廠(chǎng)商: Exar Corporation
文件頁(yè)數(shù): 5/92頁(yè)
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
標(biāo)準(zhǔn)包裝: 750
類(lèi)型: 線(xiàn)路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 3/3
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 帶卷 (TR)
xr
XRT75R03
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.8
10
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
60
104
63
RLOS_0
RLOS_1
RLOS_2
O
Receive Loss of Signal Output Indicator - Channel 0:
Receive Loss of Signal Output Indicator - Channel 1:
Receive Loss of Signal Output Indicator - Channel 2:
This output pin indicates whether or not the corresponding channel is declaring
the Loss of Signal (LOS) Defect condition.
"Low" - Indicates that the corresponding Channel is NOT currently declaring the
LOS defect condition.
"High" - Indicates that the corresponding Channel is currently declaring the LOS
defect condition.
61
103
64
RLOL_0
RLOL_1
RLOL_2
O
Receive Loss of Lock Output Indicator - Channel 0:
Receive Loss of Lock Output Indicator - Channel 1:
Receive Loss of Lock Output Indicator - Channel 2:
This output pin indicates whether or not the corresponding channel is declaring
the Loss of Lock (LOL) Condition.
"Low" - Indicates that the corresponding Channel is NOT declaring the LOL
condition.
"High" - Indicates that the corresponding Channel is currently declaring the LOL
condition.
NOTE: The Receive Section of a given channel will declare the LOL condition
anytime the frequency of the Recovered Clock (RCLK) signal differs
from that of the E3CLK input clock signal (if the channel is operating in
the E3 Mode), the DS3CLK input clock signal (if the channel is
operating in the DS3 Mode) the STS-1CLK input clock signal (if the
channel is operating in the STS-1 Mode), or that clock signal which is
derived from the SFM Clock Synthesizer block (if the chip is operating
in the Single-Frequency Mode) by 0.5% (or 5000ppm) or more.
58
112
53
RPOS_0/
RDATA_0
RPOS_1/
RDATA_1
RPOS_2/
RDATA_2
O
Receive Positive Data Output - Receive Data Output - Channel 0:
Receive Positive Data Output - Receive Data Output - Channel 1:
Receive Positive Data Output - Receive Data Output - Channel 2:
The function of these output pins depends upon whether the channel/device
has been configured to operate in the Single-Rail or Dual-Rail Mode.
Dual-Rail Mode - Receive Positive Polarity Data Output
If the channel/device has been configured to operate in the Dual-Rail Mode,
then all positive-polarity data will be output via this output pin. The negative-
polarity data will be output via the corresponding RNEG_n output pin. In other
words, the Receive Section of the corresponding Channel will pulse this output
pin "High" for one period of RCLK_n anytime it receives a positive-polarity pulse
via the RTIP/RRING input pins.
The data that is output via this pin is updated upon a user-selectable edge of
the RCLK_n output clock signal.
Single-Rail Mode - Receive Data Output
If the channel/device has been configured to operate in the Single-Rail Mode,
then all Receive (or Recovered) data will be output via this output pin.
The data that is output via this pin is updated upon a user-selectable edge of
the RCLK_n output clock signal.
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