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參數(shù)資料
| 型號： | XRT75R03IVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 44/92頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 128LQFP |
| 標準包裝： | 750 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x20） |
| 包裝： | 帶卷 (TR) |
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XRT75R03
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.8
46
Data/Clock Recovery Mode:
In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk_n out pins is the Recovered Clock signal.
6.3
B3ZS/HDB3 Decoder:
The decoder block takes the output from clock and data recovery block and decodes the B3ZS (for DS3 or
STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data
stream.
Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three
(for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV_n
output pins to indicate line code violation.
NOTE: In Dual- Rail mode, the decoder is bypassed.
6.4
LOS (Loss of Signal) Detector:
6.4.1
DS3/STS-1 LOS Condition:
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.
When the DLOS condition occurs, the DLOS_n bit is set to “1” in the status control register. DLOS condition is
cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses.
Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the
threshold as shown in the Table 10.The status of the ALOS condition is reflected in the ALOS_n status control
register.
RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output
pin is toggled “High” and the RLOS_n bit is set to “1” in the status control register.
DISABLING ALOS/DLOS DETECTION:
For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a “1” to both
ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis.
6.4.2
E3 LOS Condition:
If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the
LOS condition is detected. Loss of signal level is defined to be between 15 and 35 dB below the normal level.
If the signal drops below 35 dB for 10 to 225 consecutive pulse periods, LOS condition is declared. This is
illustrated in Figure 19.
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION REQEN SETTING LOSTHR SETTING
SIGNAL LEVEL TO DECLARE ALOS
DEFECT
SIGNAL LEVEL TO CLEAR ALOS
DEFECT
DS3
0
< 61mVpk
> 144mVpk
1
0
< 97mVpk
> 192mVpk
0
1
< 35mVpk
> 67mVpk
1
< 43mVpk
> 82mVpk
STS-1
0
< 91mVpk
> 185mVpk
1
0
< 95mVpk
> 215mVpk
0
1
< 44mVpk
> 78mVpk
1
< 44mVpk
> 91mVpk
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