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參數(shù)資料
型號(hào)： XRT75R03IVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 69/92頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 3CH 128LQFP
標(biāo)準(zhǔn)包裝： 750
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 3/3
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 帶卷 (TR)
xr
XRT75R03
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.8
68
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02
Channel 1 Address Location = 0x0A
Channel 2 Address Location = 0x12
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change of FL
Condition
Interrupt Status
Ch_n
Change of LOL
Condition
Interrupt Status
Ch_n
Change of LOS
Condition
nterrupt Status
Ch_n
Change of DMO
Condition
Interrupt Status
Ch_n
R/O
RUR
0
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
7 - 4
Unused
R/O
0
3
Change of FL Con-
dition Interrupt Sta-
tus
RUR
0
Change of FL (FIFO Limit Alarm) Condition Interrupt
Status - Ch 0:
This RESET-upon-READ bit-field indicates whether or not
the Change of FL Condition Interrupt (for Channel 0) has
occurred since the last read of this register.
0 - Indicates that the Change of FL Condition Interrupt has
NOT occurred since the last read of this register.
1 - Indicates that the Change of FL Condition Interrupt has
occurred since the last read of this register.
NOTE: The user can determine the current state of the
FIFO Alarm condition by reading out the contents
of Bit 3 (FL Alarm Declared) within the Alarm
Status Register.
2
Change of LOL
Condition Interrupt
Status
RUR
0
Change of Receive LOL (Loss of Lock) Condition Inter-
rupt Status - Ch 0:
This RESET-upon-READ bit-field indicates whether or not
the Change of Receive LOL Condition Interrupt (for Chan-
nel 0) has occurred since the last read of this register.
0 - Indicates that the Change of Receive LOL Condition
Interrupt has NOT occurred since the last read of this reg-
ister.
1 - Indicates that the Change of Receive LOL Condition
Interrupt has occurred since the last read of this register.
NOTE: The user can determine the current state of the
Receive LOL Defect condition by reading out the
contents of Bit 2 (Receive LOL Defect Declared)
within the Alarm Status Register.
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