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| 型號(hào)： | XRT75R12D |
| 廠商： | Exar Corporation |
| 英文描述： | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| 中文描述： | 第十二章通道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER |
| 文件頁數(shù)： | 110/131頁 |
| 文件大小： | 717K |
| 代理商： | XRT75R12D |
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XRT75R12D
REV. P1.0.1
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
PRELIMINARY
105
8.3.4
The overall SONET network consists of numerous "Synchronization Islands". As a consequence, whenever a
SONET signal is being transmitted from one "Synchronization Island" to another; that SONET signal will
undergo a "clock domain" change as it traverses the network. This clock domain change will result in periodic
pointer-adjustments occurring within this SONET signal. Depending upon the direction of this "clock-domain"
shift that the SONET signal experiences, there will either be periodic "incrementing" pointer-adjustment events
or periodic "decrementing" pointer-adjustment events within this SONET signal.
Regardless of whether a given SONET signal is experiencing incrementing or decrementing pointer
adjustment events, each pointer adjustment event will result in an abrupt 8-bit shift in the position of the SPE
within the STS-1 data-stream. If this STS-1 signal is transporting an "asynchronously-mapped" DS3 signal;
then this 8-bit shift in the location of the SPE (within the STS-1 signal) will result in approximately 8UIpp of jitter
within the asynchronously-mapped DS3 signal, as it is de-mapped from SONET. In “Section 8.5, A Review of
the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications” on page 106
we will discuss the "Category I Intrinsic Jitter Requirements (for DS3 Applications) per Telcordia GR-253-
CORE. However, for now we will simply state that this 8UIpp of intrinsic jitter far exceeds these "intrinsic jitter"
requirements.
In summary, pointer-adjustments events are a "fact of life" within the SONET/SDH network. Further, pointer-
adjustment events, within a SONET signal that is transporting an asynchronously-mapped DS3 signal, will
impose a significant impact on the Intrinsic Jitter and Wander within that DS3 signal as it is de-mapped from
SONET.
8.4
Clock Gapping Jitter
In most applications (in which the LIU will be used in a SONET De-Sync Application) the user will typically
interface the LIU to a Mapper Device in the manner as presented below in Figure 54.
Why are we talking about Pointer Adjustments
In this application, the Mapper IC will have the responsibility of receiving an STS-N signal (from the SONET
Network) and performing all of the following operations on this STS-N signal.
Byte-de-interleaving this incoming STS-N signal into N STS-1 signals
Terminating each of these STS-1 signals
Extracting (or de-mapping) the DS3 signal(s) from the SPEs within each of these terminated STS-1 signals.
In this application, these Mapper devices can be thought of as multi-channel devices. For example, an STS-3
Mapper can be viewed as a 3-Channel DS3/STS-1 to STS-3 Mapper IC. Similarly, an STS-12 Mapper can be
F
IGURE
54. I
LLUSTRATION
OF
THE
T
YPICAL
A
PPLICATIONS
FOR
THE
LIU
IN
A
SONET D
E
-S
YNC
A
PPLICATION
IC
DS3 to STS-N
Mapper/
Demapper
LIU
STS-N Signal
TPDATA_n input pin
TCLK_n input
De-Mapped (Gapped)
DS3 Data and Clock
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| XRT75R12DIB | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75R12 | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75R12IB | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75R12D_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET |
| XRT75R12D_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET |
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