參數(shù)資料
型號: XRT75R12D
廠商: Exar Corporation
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: 第十二章通道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁數(shù): 124/131頁
文件大小: 717K
代理商: XRT75R12D
XRT75R12D
REV. P1.0.1
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
PRELIMINARY
119
HOW MAJOR PATTERN A IS SYNTHESIZED
MAJOR PATTERN A is created (by the Mapper IC) by:
Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times.
Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times.
Figure 67 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN A
Hence, MAJOR PATTERN A consists of "(63 x 7) + (36 x 5)" = 621 clock pulses. These 621 clock pulses were
delivered over a period of "(63 x 8) + (36 x 6)" = 720 STS-1 (or 51.84MHz) clock periods.
MAJOR PATTERN B
MAJOR PATTERN B consists of three sub or minor-patterns (which we will refer to as "MINOR PATTERNS P1,
P2 and P3).
MINOR PATTERN P1, which is used to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR
PATTERN P1" as was presented above in Figure 37. Similarly, the MINOR PATTERN P2, which is also used
to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR PATTERN P2" as was presented in
Figure 38.
MINOR PATTERN P3 (which has yet to be defined) consists of a string of six (6) clock pulses, which contains
no gaps. An illustration of MINOR PATTERN P3 is presented below in Figure 68.
F
IGURE
66. I
LLUSTRATION
OF
MINOR PATTERN P2
F
IGURE
67. I
LLUSTRATION
OF
P
ROCEDURE
WHICH
IS
USED
TO
S
YNTHESIZE
MAJOR PATTERN A
1 2 3 4 5
Missing Clock Pulse
MINOR PATTERN P1
MINOR PATTERN P2
Repeats 63 Times
Repeats 36 Times
相關(guān)PDF資料
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