參數(shù)資料
型號: XRT75R12D
廠商: Exar Corporation
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: 第十二章通道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁數(shù): 66/131頁
文件大?。?/td> 717K
代理商: XRT75R12D
XRT75R12D
REV. P1.0.1
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
PRELIMINARY
61
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7,6
Reserved
5
4
3
2
1
0
TxON Ch 11
TxON Ch 10
TxON Ch 9
TxON Ch 8
TxON Ch 7
TxON Ch 6
R/W
Transmit Section ON - Channel n
This READ/WRITE bit-field is used to turn on or turn off the Transmit
Driver associated with Channel n on a per channel basis. If the user
turns on the Transmit Driver, then Channel n will transmit DS3, E3 or
STS-1 pulses on the line via the TTIP_n and TRING_ n output pins.
Conversely, if the user turns off the Transmit Driver (for channel n),
the TTIP_n and TRING_n output pins will be tri-stated.
0 - Shuts off the Transmit Driver associated with Channel n and tri-
states the TTIP_n and TRING_ n output pins.
1 - Turns on the Transmit Driver associated with Channel n.
N
OTE
:
The master TxON control (pin # P4)
must
be in a high state
(logic 1) for this operation to turn on any channel.
T
ABLE
20: C
HANNEL
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR96 (A
DDRESS
L
OCATION
= 0
X
60)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Reserved
Reserved
Channel 5
Interrupt
Enable
Channel 4
Interrupt
Enable
Channel 3
Interrupt
Enable
Channel 2
Interrupt
Enable
Channel 1
Interrupt
Enable
Channel 0
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7,6
Unused
5
4
3
2
1
0
Channel 5 Interrupt Enable
Channel 4 Interrupt Enable
Channel 3 Interrupt Enable
Channel 2 Interrupt Enable
Channel 1 Interrupt Enable
Channel 0 Interrupt Enable
R/W
Channel n Interrupt Enable Bit:
This READ/WRITE bit is used to:
To enable Channel n for Interrupt Generation at the Channel
Level
To disable all Interrupts associated with Channel n within the
XRT75R12D
This is a "master" enable bit for
each
channel. This bit allows
control on a per channel basis to signal the Host of selected error
conditions.
If a bit is cleared, no interrupts from that channel will be sent to
the Host via the INT.
If the bit is set (logic 1), any generated interrupt in channel n that
has been enabled in the Interrupt Enable register (IERn) for the
channel will activate the INT pin to the Host.
0 - Disables all Channel n related Interrupts.
1 - Enables Channel n-related Interrupts. The user
must enable
individual Channel n related Interrupts at the source level, before
they are can generate an interrupt.
相關(guān)PDF資料
PDF描述
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