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參數(shù)資料
| 型號： | XRT79L74IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | ATM NETWORK INTERFACE, PBGA456 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456 |
| 文件頁數(shù)： | 15/70頁 |
| 文件大小： | 547K |
| 代理商： | XRT79L74IB |
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PRELIMINARY
XRT79L74
REV. P1.0.0
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
13
T2
N22
V4
P23
TxNibClk1/
TxGFCMSB1/
SendFCS1
TxNibClk2/
TxGFCMSB2/
SendFCS2
TxNibClk3/
TxGFCMSB3/
SendFCS3
TxNibClk4/
TxGFCMSB4/
SendFCS4
I/O
I/O
I/O
I/O
Transmit Nibble Clock Output pin/Transmit GFC Byte - MSB Indicator Out-
put/Send FCS Value Request Input:
The function of these input/output pins depend upon whether the XRT79L74 is
configured to operate in the Clear-Channel Framer Mode, the High-Speed HDLC
Controller Mode or in the ATM Mode.
Clear-Channel Framer Mode - TxNibClk:
When operating in the Nibble-Parallel Mode the XRT79L74 will derive this clock
signal from either the TxInClk or the RxLineClk signals depending upon whether
the chip is operating in the Local-Timing or Loop-Timing Mode.
The user is advised to configure the Terminal Equipment to output the outbound
payload data to the XRT79L74 onto the TxNibn_[3:0] input pins, upon the rising
edge of these clock signals. The Transmit Payload Data Input Interface block
will sample the data, residing on the TxNibn_[3:0] line, upon the falling edge
these clock signals.
N
OTES
:
1.
For DS3 applications, the XRT79L74 will output 1176 clock pulses to
the local terminal equipment for each outbound DS3 frame.
2.
For E3, ITU-T G.832 applications, the XRT79L74 will output 1074 clock
pulses to the local terminal equipment for each outbound E3 frame.
3.
For E3, ITU-T G.751 applications, the XRT79L74 will output 384 clock
pulses to the local terminal equipment for each outbound E3 frame.
ATM Mode - TxGFCMSB:
These signals, along with TxGFC and TxGFCClk combine to function as the
Transmit GFC Nibble Field serial input port. These output signals will pulse
"High" when the MSB (most significant bit) of the GFC nibble for a given out-
bound cell is expected at the TxGFC input pins.
High-Speed HDLC Controller Mode - SendFCS:
The local terminal equipment is expected to control both these input pins, along
with the SendMSG input pins, during the construction and transmission of each
outbound HDLC frame.
These input pins are used to command the Transmit HDLC Controller block to
compute and insert the computed FCS (Frame-Check Sequence) value into the
back-end of the outbound HDLC frame, as a trailer.
If the user has configured the Transmit HDLC Controller block to compute and
insert a CRC-16 value into the outbound HDLC frame, then the local terminal
equipment is expected to hold these input pins "High" for two periods of TxHDL-
CClk. Conversely, if the user has configured the Transmit HDLC Controller block
to compute and insert a CRC-32 value into the outbound HDLC frame, then the
local terminal equipment is expected to hold these input pins "High" for four (4)
periods of TxHDLCClk.
N
OTES
:
1.
These input/output pins are inactive if the XRT79L74 has been
configured to operate in the PPP Mode.
2.
These input/output pins are inactive if the XRT79L74 has been
configured to operate in the Clear-Channel Framer/Serial mode.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
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| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
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