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參數(shù)資料
| 型號： | XRT79L74IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | ATM NETWORK INTERFACE, PBGA456 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456 |
| 文件頁數(shù)： | 27/70頁 |
| 文件大?。?/td> | 547K |
| 代理商： | XRT79L74IB |
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PRELIMINARY
XRT79L74
REV. P1.0.0
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
25
M1
H24
N5
K23
RxRED1/
RxNib1_3/
RxHDLCDat1_3
RxRED2/
RxNib2_3/
RxHDLCDat2_3
RxRED3/
RxNib3_3/
RxHDLCDat3_3
RxRED4/
RxNib4_3/
RxHDLCDat4_3
O
O
O
O
Receive Section Red Alarm Indicator/Receive Nibble Interface Output pin -
Bit 3/Receive HDLC Controller Data Bus output pin - Bit 3:
The function of this output pin depends upon whether the XRT79L74 has been
configured to operate in the Clear-Channel Framer/Nibble-Parallel Mode, the
High-Speed HDLC Controller Mode, or in some other mode.
Clear-Channel Framer/Nibble-Parallel Mode - RxNib_3:
The XRT79L74 will output Received data from the remote terminal equipment
to the local terminal equipment via this pin, along with RxNib_0 through
RxNib_2. This particular output pin functions as the LSB. The data at this pin is
updated on the rising edge of the RxClk output signal. Hence, the user’s local
terminal equipment should sample this signal upon the falling edge of RxClk.
High-Speed HDLC Controller Mode - RxHDLCDat_3:
This output pin along with RxHDLCDat_[7:4] and RxHDLCDat_[2:0] functions
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via this output data bus,
upon the rising edge of the RxHDLCClk output signal. Hence, the user’s local
terminal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signal.
Other Modes - RxRED - RED Alarm/Defect Indicator Output pin:
The XRT79L74 device will assert this output pin (e.g., toggle it "high") in
order to indicate that the Receive DS3/E3 Framer block is currently
declaring at least one of the following defect conditions.
LOS - Loss of Signal Defect Condition
OOF - Out of Frame Defect Condition
AIS - Alarm Indication Signal Defect Condition.
The XRT79L74 device will negate this output pin (e.g., toggle it "low")
anytime that the Receive DS3/E3 Framer block is NOT currently
declaring any of the above-mentioned defect conditions.
M3
H22
P4
K25
RxOOF1/
RxNib1_1/
RxHDLCDat1_1
RxOOF2/
RxNib2_1/
RxHDLCDat2_1
RxOOF3/
RxNib3_1/
RxHDLCDat3_1
RxOOF4/
RxNib4_1/
RxHDLCDat4_1
O
O
O
O
Receive Out of Frame Indicator/Receive Nibble Interface Output pin - Bit 1/
Receive HDLC Controller Data Bus Output pin - Bit 1:
The function of these output pins depend upon whether the XRT79L74 has
been configured to operate in the Clear-Channel Framer/Nibble-Parallel Mode
or the High-Speed HDLC Controller Mode.
Clear-Channel Framer/Nibble-Parallel Mode - RxNib_1:
The XRT79L74 will output Received data from the remote terminal equipment
to the local terminal equipment via these pins, along with RxNibn_0, RxNibn_2
and RxNibn_3: These particular output pins function as the LSB. The data at
these pins are updated on the rising edge of the RxClk output signals. Hence,
the user’s local terminal equipment should sample these signals upon the falling
edge of RxClk.
High-Speed HDLC Controller Mode - RxHDLCDat_1:
These output pins along with RxHDLCDatn_[7:2] and RxHDLCDatn_0 functions
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via these output data bus,
upon the rising edge of the RxHDLCClk output signals. Hence, the user’s local
terminal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signals.
All other Modes - RxOOF:
The UNI Receive DS3 Framer will assert these output signals whenever it has
declared an Out of Frame (OOF) condition with the incoming DS3 frames.
These signals are negated when the framer correctly locates the F- and M-bits
and regains synchronization with the DS3 frame.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
相關(guān)PDF資料 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000D | 制造商:EXAR 制造商全稱:EXAR 功能描述:CLOCK SYNCHRONIZER/ADAPTER FOR COMMUNICATIONS |
| XRT8000ES | 功能描述:鎖相環(huán) - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8000ID | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
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