- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376462 > XRT79L74IB (EXAR CORP) 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC PDF資料下載
參數(shù)資料
| 型號： | XRT79L74IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | ATM NETWORK INTERFACE, PBGA456 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456 |
| 文件頁數(shù)： | 24/70頁 |
| 文件大小： | 547K |
| 代理商： | XRT79L74IB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁
XRT79L74
REV. P1.0.0
PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
22
C8
B8
A8
E9
C9
TxUAddr_0
TxUAddr_1
TxUAddr_2
TxUAddr_3
TxUAddr_4
I
Transmit UTOPIA Address Bus/Transmit POS-PHY Address Bus:
The exact function of these input pins depends upon whether the XRT79L74
device has been configured to operate in the ATM UNI or PPP Modes.
ATM UNI Mode -TxUAddr[4:0] - Transmit UTOPIA Address Bus:
These input pins comprise the Transmit UTOPIA Address Bus input pins. The
Transmit UTOPIA Address Bus is only in use when the XRT79L74 is operating in
the Multi-PHY mode. Whenever the ATM Layer processor wishes to poll or write
data to a particular UNI (PHY-Layer) device, it will provide the address of the "tar-
get UNI" on the Transmit UTOPIA Address Bus. The contents of the Transmit
UTOPIA Address Bus input pins are sampled on the rising edge of TxUClk clock
signal. The Transmit UTOPIA Interface block will compare the data on the
Transmit UTOPIA Address Bus with the pre-programmed UTOPIA Address
value (which was loaded into the XRT79L74 device by writing the appropriate
data into both the "Transmit UTOPIA Port Address" Register (Address = 0x0593)
and the "Transmit UTOPIA Port Number" Register (Address = 0x0597). If these
two values are identical and the TxUENB* input pin is asserted, then the TxU-
Clav output pin will be driven to the appropriate state (based upon the TxFIFO fill
level) for the Cell Level handshake mode of operation. If these two values do not
match, then the Transmit UTOPIA Interface block will continue to tri-state the
"TxUClav" output pin.
N
OTE
:
These input pins are only active if the XRT79L74 device has been
designed into a "Multi-PHY" Application. If the user intends to design the
XRT79L74 into a "Single-PHY" Application, then he/she should tie these
input pins to GND.
PPP Mode - TxPAddr[4:0] - Transmit POS-PHY Interface Address Bus Input
Pins:
These input pins comprise the Transmit POS-PHY Address Bus input pins.
Whenever the Link Layer Processor wishes to poll or write data to a particular
PHY-Layer device, it will provide the address of the "target PHY-Layer device" on
the Transmit POS-PHY Address Bus. The contents of the Transmit POS-PHY
Address Bus input pins are sampled on the rising edge of TxPClk. The
XRT79L74 device will compare the data on the Transmit POS-PHY Address Bus
with the pre-programmed POS-PHY Address value (which was loaded into the
XRT79L74 device by writing the appropriate data into the "Transmit POS-PHY
Interface - Transmit Control Register - Byte 0" (Address = 0x0582). If these two
values are identical and the "TxPENB*" input pin is asserted, then the TxPPA
output pin will be driven to the appropriate state (based upon the TxFIFO fill
level). If these two values do not match, then the Transmit POS-PHY Interface
block will continue to tri-state the "TxPPA" output pin.
N
OTE
:
These input pins are only active if the XRT79L74 device has been
configured to operate in either the ATM UNI or PPP Modes. The user
should tie these input pins to GND if he/she wishes to operate the
XRT79L74 device in either the "Clear-Channel Framer" or "High-Speed
HDLC Controller" Modes.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT8000ID | Clock Synchronizer/Adapter for Communications |
| XRT8000 | Clock Synchronizer/Adapter for Communications(用于通訊的時鐘同步設(shè)備/調(diào)整器) |
| XRT8001 | WAN Clock for T1 and E1 Systems |
| XRT8001ID | WAN Clock for T1 and E1 Systems |
| XRT8001IP | WAN Clock for T1 and E1 Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000D | 制造商:EXAR 制造商全稱:EXAR 功能描述:CLOCK SYNCHRONIZER/ADAPTER FOR COMMUNICATIONS |
| XRT8000ES | 功能描述:鎖相環(huán) - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8000ID | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。