參數(shù)資料
型號(hào)： XRT79L74IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
中文描述： ATM NETWORK INTERFACE, PBGA456
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456
文件頁(yè)數(shù)： 19/70頁(yè)
文件大?。?/td> 547K
代理商： XRT79L74IB
PRELIMINARY
XRT79L74
REV. P1.0.0
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
17
T1
N23
V3
P22
TxCellTxed1/
TxNibFrame1/
ValidFCS1
TxCellTxed2/
TxNibFrame2/
ValidFCS2
TxCellTxed3/
TxNibFrame3/
ValidFCS3
TxCellTxed4/
TxNibFrame4/
ValidFCS4
O
O
O
O
Transmit Cell Generator indicator/Transmit Nibble Frame Indicator/Valid
FCS Indicator output:
The function of these output pins depend upon whether the XRT79L74 has been
configured to operate in the ATM Mode, the Clear-Channel Framer Mode or in
the High-Speed HDLC Controller Mode.
ATM Mode - TxCellTxed:
This output pin pulses "High" each time the Transmit Cell Processor transmits a
cell to either the Transmit PLCP Processor or the Transmit DS3/E3 Framer block.
Clear-Channel Framer Mode - TxNibFrame:
These output pins pulse "High" when the last nibble of a given DS3 or E3 frame
is expected at the TxNibn[3:0] input pins.
The purpose of these output pins are to alert the local terminal equipment that it
needs to begin the transmission of a new DS3 or E3 frame to the XRT79L74.
N
OTE
:
These output pins are not active if the XRT79L74 is configured to operate
in the Serial-Mode.
High-Speed HDLC Controller Mode - ValidFCS:
The combination of the RxIdle and ValidFCS output signals are used to convey
information about data that is being output via the Receive HDLC Controller out-
put Data bus (RxHDLCDatn_[7:0]).
If RxIdle = "High":
The Receive HDLC Controller block will drive these output pins "High" anytime
the flag sequence octet (0x7E) is present on the RxHDLCDatn[7:0] output data
bus.
If RxIdle and ValidFCS are both "High":
The Receive HDLC Controller block has received a complete HDLC frame, and
has determined that the FCS value within this HDLC frame are valid.
If RxIdle is "High" and ValidFCS is "Low":
The Receive HDLC Controller block has received a complete HDLC frame, and
has determined that the FCS value within this HDLC frame is invalid.
If RxIdle is "High" and ValidFCS is "Low":
The Receive HDLC Controller block has received an ABORT sequence.
D11
TxPERR
I
Transmit Error Indicator from Link Layer:
This input signal is used to indicate that the current packet is ABORTED and
must be discarded. This input pin should only be asserted when the last byte (or
word) is be written onto the TxPData[15:0] input pins.
If the Link Layer Processor block identifies a given "outbound" PPP Packet as
being "erred", then the Transmit PPP Packet Processor block will transmit this
particular packet (to the remote terminal equipment) as an Aborted Packet.
N
OTE
:
This input pin is only active if the XRT79L74 has been configured to
operate in the PPP Mode.
C11
TxPEOP
I
Transmit POS-PHY Interface - End of Packet:
The link layer processor toggles this output pin "High" whenever the Link Layer
Processor is writing the last byte (or word) of a given Packet into the Transmit
POS-PHY Data Bus (e.g., the TxPData[15:0] data input pins).
N
OTES
:
1.
This input pin is only valid when the XRT79L74 is configured to operate
in the PPP Mode.
2.
This input pin is only valid when the Transmit POS-PHY Interface -
Write Enable Input pin (TxPEn) is asserted.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
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