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參數(shù)資料
| 型號： | XRT79L74IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | ATM NETWORK INTERFACE, PBGA456 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456 |
| 文件頁數(shù)： | 38/70頁 |
| 文件大小： | 547K |
| 代理商： | XRT79L74IB |
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XRT79L74
REV. P1.0.0
PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
36
C16
RxUEN/
RxPEN
I
Receive UTOPIA Interface - Output Enable/Receive POS-PHY Interface -
Output Enable:
The function of this output pin depends upon whether the XRT79L74 has been
configured to operate in the ATM UNI or PPP mode.
ATM UNI Mode - RxUEN:
This active-low input signal is used to control the drivers of the Receive UTOPIA
Data Bus. When this signal is "High" (negated) then the Receive UTOPIA Data
Bus is tri-stated. When this signal is asserted, then the contents of the byte or
word that is at the front of the RxFIFO will be popped and placed on the Receive
UTOPIA Data bus on the very next rising edge of RxUClk.
PPP Mode - RxPEN:
This active-low input signal is used to control the drivers of the Receive POS-
PHY Data Bus. When this signal is "High" (negated) then the Receive POS-
PHY Data Bus is tri-stated. When this signal is asserted, then the contents of
the byte or word that is at the front of the RxFIFO will be popped and placed on
the Receive POS-PHY Data bus on the very next rising edge of RxPClk.
N
OTE
:
The user should tie these input pins to GND, if he/she intends to operate
the XRT79L74 device in either the Clear-Channel Framer or High-
Speed HDLC Controller Modes.
A16
RxUSoC/
RxPSOP/RxP-
SOC
O
Receive UTOPIA Interface - Start of Cell Indicator/Receive POS-PHY Inter-
face - Start of Packet Indicator:
The function of this output pin depends upon whether the XRT79L74 has been
configured to operate in the ATM UNI or in the PPP Mode.
ATM UNI Mode - RxUSoC:
This output pin allows the ATM Layer Processor to determine the boundaries of
the ATM cells that are output via the Receive UTOPIA Data bus. The Receive
UTOPIA Interface block will assert this signal when the first byte (or word) of a
new cell is present on the Receive UTOPIA Data Bus; RxUData[15:0].
PPP Mode - RxPSOP:
This output pin allows the Link Layer Processor to determine the boundaries of
the PPP packets that are output via the Receive POS-PHY Data Bus. The
Receive POS-PHY Interface block will assert this signal when the first byte (or
word) of a new packet is present on the Receive POS-PHY Data Bus, RxP-
Data[15:0].
PPP Chunk Mode - RxPSOC - Receive Start of Chunk Indicator Output
(Chunk Mode):
If the XRT79L74 device has been configured to operate in the "Chunk Mode,
then the Receive POS-PHY Interface block will pulse this output pin "high" coin-
cident to whenever it outputs the very first byte (or 16-bit word) of a given Chunk
onto the Receive POS-PHY Data Bus (RxPData[15:0]) output pins. The
Receive POS-PHY Interface block will keep this output pin "low" at all other
times.
N
OTE
:
In the "PPP Chunk" Mode, the RxPSOF output pin will function as the
"Start of Packet" Output Indicator pin.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
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