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參數(shù)資料
| 型號： | XRT8001ID |
| 廠商： | EXAR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | WAN Clock for T1 and E1 Systems |
| 中文描述： | 8001 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO18 |
| 封裝： | 0.300 INCH, SOIC-18 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 1054K |
| 代理商： | XRT8001ID |
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XRT8001
20
Rev. 1.01
LDETDIS[2:1]
00
Signal output via the LOCKDET Signal
The LOCK Condition of PLL1 AND PLL2
With this selection, the LOCKDET output pin will be “high” if either one of the
following conditions are true.
a.
If both PLL1 and PLL2 are in the “LOCK” condition, (
applies if both PLL1 and
PLL2 are enabled
) or
b.
If the only enabled PLL is in the “LOCK” condition (
applies only if one of the
PLLs are enabled
).
The LOCK Condition of PLL2 Only
With this selection, only the “LOCK” state of PLL2 will be reflected in the LOCKDET
output pin.
01
LOCKDET = “high” if PLL2 is in “LOCK”.
LOCKDET = “l(fā)ow” if PLL2 is out of “LOCK”.
The LOCK Condition of PLL1 Only
With this selection, only the “LOCK” state of PLL1 will be reflected in the LOCKDET
output pin.
10
LOCKDET = “high” if PLL1 is in “LOCK”.
LOCKDET = “l(fā)ow” if PLL1 is out of “LOCK”.
LOCKDET will be unconditionally pulled to “LOW”
11
Table 3. Relationship Between the Values of the LDETDIS[2:1]
Bit-Fields and the Meaning of the LOCKDET Output Signal
4.0 Instructions for Configuring the XRT8001 WAN
Clock
As mentioned earlier, the XRT8001 WAN Clock can be
configured to operate in the following modes:
The “Forward/Master” Mode
The “Reverse/Master” Mode
The “Fractional T1/E1 Reverse/Master” Mode
The “E1 to T1 – Forward/Master” Mode
The “High Speed – Reverse” Mode
The “Forward/Slave” Mode
A detailed description of the operation and the configu-
ration steps for each of these configurations follows.
4.1 The “Forward/Master” Mode.
When the XRT8001 WAN Clock has been configured to
operate in the “Forward/Master” Mode, then it will
accept an “N x 1.544MHz” or an “N x 2.048MHz” clock
signal via the “Reference Clock” input at FIN (pin 3);
where “N” can range anywhere between 1 and 16. In
response to this clock signal, the XRT8001 WAN Clock
will output either a “K x 56kHz” or a “K x 64kHz” clock
signal, via the Clock Output pins (CLK1 and/or CLK2).
A simple illustration of the XRT8001 WAN Clock,
operating in the “Forward/Master” Mode is shown in
figure 13.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT8001ID-F | 功能描述:鎖相環(huán) - PLL 3.3V-5V temp -45 to 85C RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8001ID-F | 制造商:Exar Corporation 功能描述:WAN Clock IC |
| XRT8001IDTR-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8001IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:WAN Clock for T1 and E1 Systems |
| XRT8001IP-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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