參數(shù)資料
型號: XRT8001ID
廠商: EXAR CORP
元件分類: 時鐘及定時
英文描述: WAN Clock for T1 and E1 Systems
中文描述: 8001 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO18
封裝: 0.300 INCH, SOIC-18
文件頁數(shù): 30/48頁
文件大?。?/td> 1054K
代理商: XRT8001ID
XRT8001
30
Rev. 1.01
Value of “M”
Value to be Written into
Command Register CR2
0000X
0001X
001XX
X1XX or 1XXX
1
2
4
8
Table 7. Relationship Between the Value of
“M” and the Value to Be Written into Command
Register CR2 (in Order to Configure the “CLK1”
Output Frequency)
Note:
The expression “X” indicates a “Don’t Care” value for
that particular bit-field.
Command Register, CR2 (Address = 0x02)
D4
D3
D2
SEL14
SEL13
SEL12
Value from Table 7
D1
D0
SEL11
SEL10
Step 5
– Specify the value for “M” (e.g., as in the “M x
2.048MHz” clock signal) which is to be the output on
the “CLK2” output pin.
This is accomplished by reviewing Table 8, and deter-
mining the 5-bit binary value which corresponds with
the desired value of “M”. Afterwards, the user should
write this value into Command Register, CR3.
Value of “M”
Value to be Written into
Command Register CR3
0000X
0001X
001XX
X1XXX or 1XXXX
1
2
4
8
Table 8. Relationship Between the Value of
“M” and the Value to Be Written into Command
Register CR3 (in Order to Configure the “CLK2”
Output Frequency)
Note:
The expression “X” indicates a “Don’t Care” value
for that particular bit-field.
Command Register, CR3 (Address = 0x03)
D4
D3
D2
SEL24
SEL23
SEL22
Value from Table 8
D1
D0
SEL21
SEL20
Step 6
– Enable any of the following output signals as
appropriate: “SYNC”, “CLK1”, “CLK2” and
“LOCKDET”.
This is accomplished by writing a “1” into the corre-
sponding bit-fields, within Command Register CR4, as
illustrated below:
Command Register CR4, (Address = 0x04)
D4
D3
SYNCEN
CLK1EN
CLK2EN
1
1
D2
D1
D0
LDETDIS2
0
LDETDIS1
0
1
6.8 The "Forward/Slave" Mode
When the XRT8001 WAN Clock has been configured to
operate in the “Forward/Slave” Mode, then it will accept
an 8kHz clock signal via the “Reference Clock” input at
FIN (pin 3). In response to this clock signal, the
XRT8001 WAN Clock will output either a “L x 56kHz” or
“L x 64kHz” clock signal via the “Clock Output pins”
(CLK1 and CLK2); where L can range in value from 1 to
32.
A simple illustration of the XRT8001 WAN Clock
operating in the "Forward/Slave" Mode” is presented in
Figure 18.
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