參數(shù)資料
型號(hào): XRT8001ID
廠商: EXAR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: WAN Clock for T1 and E1 Systems
中文描述: 8001 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO18
封裝: 0.300 INCH, SOIC-18
文件頁(yè)數(shù): 9/48頁(yè)
文件大小: 1054K
代理商: XRT8001ID
XRT8001
9
Rev. 1.01
CSB
SCLK
SDI
R/W
A0
A1
A2
A3
0
0
A6
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
0
0
0
SDO
High Z
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Notes:
A4 and A5 are always “0”.
R/W = “1” for “Read” Operations
R/W = “0” for “Write” Operations
- Denotes a “don’t care” value
Simplified Interface Option
The user can simplify the design of the circuitry
connecting to the Microprocessor Serial Interface by
tying both the SDO and SDI pins together, and reading
data from and/or writing data to this “combined” signal.
This simplification is possible because only one of
these signals are active at any given time. The inactive
signal will be tri-stated.
Figure 6. Microprocessor Serial Interface Data Structure
Write Operation
Once the last address bit (A3) has been clocked into
the SDI input, the “Write” operation will proceed through
an idle period, lasting three SCLK periods. Prior to the
rising edge of SCLK Cycle # 9 (see Figure 6) the user
must begin to apply the 8-bit data word, that he/she
wishes to write to the Microprocessor Serial Interface,
onto the SDI input pin. The Microprocessor Serial
Interface will latch the value on the SDI input pin, on the
rising edge of SCLK. The user must apply this word (D0
through D7) serially, in ascending order with the LSB
first.
相關(guān)PDF資料
PDF描述
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