參數(shù)資料
型號: XRT8001ID
廠商: EXAR CORP
元件分類: 時鐘及定時
英文描述: WAN Clock for T1 and E1 Systems
中文描述: 8001 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO18
封裝: 0.300 INCH, SOIC-18
文件頁數(shù): 42/48頁
文件大?。?/td> 1054K
代理商: XRT8001ID
XRT8001
42
Rev. 1.01
Command Register, CR1 (Address = 0x01)
D4
D3
M4
M3
0
0
NOTE:
In order to synthesize and output a clock signal via
the “CLK2” output, the user must write a “1” into the “D0
(PL2EN) bit-field within Command Register, CR1, as
illustrated above
.
D2
M2
0
D1
M1
0
D0
PL2EN
1
The values within Command Registers CR2 and CR3
are “don’t care”.
STEP 4
– Enable the desired output signals: SYNC,
CLK1, CLK2, and LOCKDET.
This is accomplished by writing a “1” into the corre-
sponding bit-field, within Command Register, CR4, as
illustrated below.
Command Register, CR4 (Address = 0x04)
D4
D3
SYNCEN
CLK1EN CLK2EN LDETDIS2 LDETDIS1
1
1
1
D2
D1
D0
1
1
Once the user has executed these four (4) steps, then
the circuitry in Figure 24 is configured to accept a
1.544MHz clock signal (from the T1/E1 LIU) and
synthesize a 1.544MHz clock signal.
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PDF描述
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