參數(shù)資料
型號: XRT8001ID
廠商: EXAR CORP
元件分類: 時鐘及定時
英文描述: WAN Clock for T1 and E1 Systems
中文描述: 8001 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO18
封裝: 0.300 INCH, SOIC-18
文件頁數(shù): 31/48頁
文件大?。?/td> 1054K
代理商: XRT8001ID
XRT8001
31
Rev. 1.01
6.9 Configuring the XRT8001 WAN Clock into the
“Forward/Slave” Mode.
The user can configure the XRT8001 WAN Clock to
operate in the “Forward/Slave Mode” by executing the
following steps:
Step 1
– Configure the XRT8001 to operate in the
“SLAVE” Mode by pulling the MSB input pin (pin 8) to
GND.
Step 2
– Refer to Table 2B and write the value that
corresponds to the desired "Forward/Slave" Mode into
Bits D[4:1] within Command Register CR0.
Step 3
– Define the values for L, for the CLK1 output
by writing the appropriate value into the CR2 register.
This is achieved by writing the value “L – 1” into this
register.
Notes:
1.
For example, if the user writes “00000” into this regis-
ter, then the XRT8001 device will output a 64kHz
signal via the CLK1 output pin.
If the user intends to output data via CLK1, then he/she
must ensure that the PL1EN bit-field within Command
Register CR0 is set to “1”.
2.
Figure 18. Illustration of the XRT8001 WAN Clock operating in the
“Forward/Slave" Mode
Step 4- Define the value for L, for the CLK2 output
by writing the appropriate value into the CR3 regis-
ter. This is achieved by writing the value “L – 1”
into this register.
Note:
If the user intends to output data via CLK2, then he/
she must ensure that the PL2EN bit-field within Command
Register CR1 is set to “1”.
S
tep
5 – Set the CLK1EN and CLK2EN bit-fields,
within Command Register CR4 to 1 in order to
enable the output drivers for CLK1 and CLK2, as
illustrated below.
XRT8001
WAN Clock
FIN
CLK1
CLK2
8kHz
L x 56kHz
to
L x 64kHz
1 < L < 32
L x 56kHz
to
L x 64kHz
1 < L < 32
Command Register CR4
D4
SYNCEN
CLK1EN
x
D3
D2
D1
X
0
D0
X
0
CLK2EN
1
1
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