參數(shù)資料
型號(hào): XRT8001IP
廠商: EXAR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: WAN Clock for T1 and E1 Systems
中文描述: 8001 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP18
封裝: 0.300 INCH, PLASTIC, DIP-18
文件頁(yè)數(shù): 22/48頁(yè)
文件大?。?/td> 1054K
代理商: XRT8001IP
XRT8001
22
Rev. 1.01
Step 3
– Upon reviewing Table 4, write the listed value
(under the “Value to Write to D4 – D1 in CR0” Register
Column) into the D4 through D1 bit-fields within Com-
mand Register CR0, as illustrated below.
Note:
If the user wishes to output a clock signal via the
CLK1 output signal, then he/she should also write a “1” into
the “PL1EN” bit-field within Command Register CR0.
This step configures the XRT8001 to operate in the
“Forward/Master” Mode.
Step 4
– Next, you need to specify the value for “N”
(e.g., as in the “N x 1.544MHz” or “N x 2.048MHz” clock
signal which is to be applied to the “FIN” input pin.)
In order to specify the value for “N”, one needs to write
the value of “N - 1” (in binary format) into the “D4 through
D1” bits within Command Register CR1, as illustrated
below.
Command Register CR0 (Address = 0x00)
D4
D3
D2
IOC4
IOC3
IOC2
Value to Write to D4 – D1 in CR0
D1
IOC1
D0
PL1EN
X
Command Register, CR1 (Address = 0x01)
D4
D3
D2
M4
M3
M2
Value of “N - 1” (in Binary Format)
D1
M1
D0
PL2EN
X
For example, if the user wishes to configure the
XRT8001 to accept a 1.544MHz clock signal, via the
“FIN” input pin (e.g., N = 1), then the user should write
in the value “0”, into Command Register CR1.
Note:
If the user wishes to output a clock signal via the
CLK2 output signal, then he/she should also write a “1” into
the “PL2EN” bit-field within Command Register CR1.
Step 5
– Specify the value of “K” (e.g., as in the “K x
56kHz” or “K x 64kHz” clock signal which is to be output
via the CLK1 output signal).
Command Register, CR2 (Address = 0x02)
D4
D3
D2
SEL14
SEL13
SEL12
Value of “K - 1” (in Binary Format).
D1
D0
SEL11
SEL10
For example, if one wishes to configure the XRT8001
to output a clock signal of either “56kHz” or “64kHz”
(e.g., where “K” = 1) via the CLK1 output pin, then he/
she should write the value “0”, into Command Register
CR2.
Step 6
– Specify the value of “K” (e.g., as in the “K x
56kHz” or “K x 64kHz” clock signal which is to be output
via the CLK2 output signal).
In order to specify the value for “K”, one needs to write
the value of “K - 1” (binary format) into Command
Register CR3, as illustrated below.
Command Register, CR3 (Address = 0x03)
D4
D3
D2
SEL24
SEL23
SEL22
Value of “K - 1” (in Binary Format).
D1
D0
SEL21
SEL20
For example, if one wishes to configure the XRT8001
to output a clock signal of either “1.792MHz” or
“2.048MHz” (e.g., where “K” = 32) via the CLK2 output
pin, then he/she should write the value “31” (or “1 1 1
1 1” in binary format) into Command Register CR3.
Step 7
– Enable any of the following output signals as
appropriate: “SYNC”, “CLK1”, “CLK2” and
“LOCKDET”.
This is accomplished by writing a “1” into the corre-
sponding bit-fields, within Command Register CR4, as
illustrated below.
Command Register CR4, (Address = 0x04)
D4
D3
SYNCEN
CLK1EN
CLK2EN
1
1
D2
D1
D0
LDETDIS2
0
LDETDIS1
0
1
Note:
For information on the “LDETDIS1” and “LDETDIS2”
bit-fields, please see Table 3.
In order to specify the value for “K”, one needs to write
the value of “K - 1” (in binary format) into Command
Register CR2, as illustrated below.
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