參數(shù)資料
型號(hào): XRT8001IP
廠商: EXAR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: WAN Clock for T1 and E1 Systems
中文描述: 8001 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP18
封裝: 0.300 INCH, PLASTIC, DIP-18
文件頁數(shù): 6/48頁
文件大?。?/td> 1054K
代理商: XRT8001IP
XRT8001
6
Rev. 1.01
AC ELECTRICAL CHARACTERISTICS (See Figure 4.)
Symbol
Parameter
t1
Input Frequency
Min.
0.008
0.008
12
Typ.
Max. Units
32.7
32.7
Conditions
MHz
MHz
ns
3.3V
5V
t2
Minimum Input Signal “High” to
“Low” Duration
Output Frequency
Duty Cycle
Jitter Added 8kHz – 40kHz
t3
t6
1
t7
4
56
47.5
16,384
52.5
0.02
0.02
kHz
%
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
ms
ms
ns
ns
%
50
0.01
0.01
0.03
0.03
0.03
0.035
VCC/2 switch point, 30pF Load
3.3V, Output = 1.544MHz (0.025 UI)
3
5V, Output = 1.544MHz (0.025 UI)
3
3.3V, Output = 1.544MHz (0.025 UI)
3
5V, Output = 1.544MHz (0.025 UI)
3
3.3V, Output = 1.544MHz (0.05 UI)
3
5V, Output = 1.544MHz (0.05 UI)
3
3.3V, Output = 2.048MHz (1.5 UI)
3
5V, Output = 2.048MHz (1.5 UI)
3
3.3V, Output = 2.048MHz (0.2 UI)
3
5V, Output = 2.048MHz (0.2 UI)
3
3.3V
5V
30pF load measured at 20/80%
30pF load measured at 20/80%
VCC/2 switch point
t7
4
Jitter Added 10Hz – 40kHz
t7
4
Broadband Jitter
0.05
0.05
0.07
0.07
0.03
0.03
40
40
10ns
10ns
60
t7
4
Jitter Added 20Hz – 100kHz
0.01
t7
4
Jitter Added 18kHz – 100kHz
0.007
t8
Capture Time
t9
t10
t11
2
t12
t13
t14
Clock Output Rise Time
Clock Output Fall Time
SYNC Output Signal Duty Cycle
SYNC Ouput Signal + Cycle
SYNC Output Signal – Cycle
Delay Time between the rising
edge of of SYNC and the Rising
edge of CLK1 and CLK2
CSB Low to Rising Edge of SCLK
Setup Time
CSB High to Rising Edge of SCLK
Hold Time
SDI to Rising Edge of SCLK Setup Time
SDI to Rising Edge of SCLK Hold Time
SCLK “Low” Time
SCLK “High” Time
SCLK Period
CSB Low to Rising Edge of SCLK
Hold Time
CSB “Inactive” Time
Falling Edge of SCLK to SDO Valid Time
Falling Edge of SCLK to SDO Invalid Time
Falling Edge of SCLK, or rising edge
of CSB to High Z
Rise/Fall time of SDO Output
F
IN
Duty Cycle
40
t-20
t+20
ns
See Table 8 for values of “t”
t21
50
ns
t22
20
ns
t23
t24
t25
t26
t27
t28
50
50
240
240
500
50
ns
ns
ns
ns
ns
ns
t29
t30
t31
t32
250
ns
ns
ns
ns
200
100
100
t33
PW
MIN
40
ns
ns
12
Notes:
1
2
3
Specifications from AT&T Publication 62411 and ITU-T
Recommendations G-823 (for 1.544MHz and (2.048MHz).
t7 is guaranteed by characterization, not tested.
4
t6 =
t4
(t4 + t5)
t11 =
t12
(t12 + t13)
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