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參數(shù)資料
| 型號(hào)： | XRT81L27IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 15/30頁 |
| 文件大?。?/td> | 194K |
| 代理商： | XRT81L27IV |
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XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
13
FUNCTIONAL DESCRIPTION
The XRT81L27 operates in two modes; Hardware or
Host. As described below, Hardware mode allows the
chip to be controlled by digital signals to put it into
various configurations. The Host mode allows a Micro
to control these configurations through a serial inter-
face.
THE HARDWARE MODE
The XRT81L27 is placed into the Hardware mode by
connecting the Mode pin (pin 32) to VDD ("High").
When the chip is in the Hardware mode the following
control pins are active: RST/LBEN (pin 3), SDO/LBM
(pin 47), SDI/B1 (pin 48), SClk/B2 (pin 49), CS/B3
(pin 50), SR/DR (pin 69), RClkP (pin 65), TClkP (pin
66). The TAOSx pins (40, 46, 51, 108, 112, 113, 117)
are used to insert "all ones" data into the individual
channels. In addition, the PDTx pins (6, 11, 22, 27,
75, 86, 91) are active in both Hardware and Host
modes to control the individual Transmit line buffers.
The RST/LBEN pin (3) is used to enable Loopback
mode. When pulled "Low" Loopback is active. SDO/
LBM (pin 47) selects the type of Loopback. With LBM
(pin 47) "High", Analog Loopback is active (Terminal
Equipment Transmit through the channel(s) selected
and back to the Receive out pins). If LBM is "Low",
Remote Loopback is selected (Receive line through
the channel and back out onto the Transmit TIP/RING
buffer onto the Transmit line. Digital Local Loopback
is not supported in Hardware mode.
Pins B1, B2, and B3 are used to select the desired
Loopback channel as shown on page 5. This allows
the selection of any one of the seven channels or all
seven. SR/DR (pin 69) is used to select between Sin-
gle Rail or Dual Rail mode for data to and from the
Terminal equipment. With pin 69 tied "High", Single
Rail is selected. Dual Rail will be active if the pin is
pulled "Low". An internal pull-down will accomplish
that if the if the pin is left open.
With RClkP "Low" or open, all RPOS & RNEG lines
are updated on the falling edge of RClk. When RClkP
is "High", RPOS & RNEG are updated on the rising
edge of RClk. In Host mode the update edge is con-
trolled by the RClkP bit in the Global control latch
(R0, bit 1).
When TClkP is "Low" or open, all TPOS & TNEG
lines are sampled on the falling edge of TCLK. When
TClkP is "High", TPOS & TNEG are sampled on the
rising edge of TClk. In Host mode the sampling edge
is controlled by the TClkP bit in the Global control
register (R0, bit 0).
If the TAOSX pin of a channel is pulled "High", the
channel will Transmit all ones using the MClk signal
for a timing reference. If "Low", "normal" data will be
transmitted using the TClk.
THE HOST MODE
To configure the XRT81L27 to operate in the HOST
Mode, connect the MODE input pin (pin 32) to
Ground or leave unconnected.
When the XRT81L27 is operating in the HOST Mode,
the Microprocessor Serial Interface block is enabled.
Configuration selections are made by writing the ap-
propriate data into the on-chip Command Registers
via the Microprocessor Serial Interface.
1.0
THE MICROPROCESSOR SERIAL INTER-
FACE (MSI)
The on-chip Command Registers of the XRT81L27
E1 Line Interface Unit IC are accessed to configure
the XRT81L27 into a variety of modes. This section
describes how to use the Microprocessor Serial Inter-
face and the Command Registers.
1.1
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
DESCRIP
-
TION
.
The XRT81L27 MSI uses a simple four wire interface
that is compatible with most microcontrollers. Either
hardware blocks in the micro can supply the data or
“bit-banging” can be used. This interface consists of
the following signals:
CS
(pin 50) Chip Select (Active Low)
SCLK
(pin 49) Serial Clock
SDI
(pin 48) Serial Data Input
SDO
(pin 47) Serial Data Output
USING THE MICROPROCESSOR SERIAL INTER-
FACE (MSI)
The user performs Read and Write operations to the
on-chip Command Registers (via the MSI) in two dis-
tinct phases:
The “Selection Phase”, and
The “Data Phase”
The procedure for performing each of these phases is
presented below.The following descriptions for using
the Microprocessor Serial Interface are best under-
stood by referring to the diagram in Figure 6.
1.1.1
Selection Phase
In order to use the Microprocessor Serial Interface, a
chip select CS signal must be supplied to the CS in-
put pin. It is important to assert the CS pin (“Low”) at
least 50ns prior to the first rising edge of the clock
signal.
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