參數(shù)資料
型號： XRT81L27IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
中文描述： DATACOM, PCM TRANSCEIVER, PQFP128
封裝： TQFP-128
文件頁數(shù)： 3/30頁
文件大?。?/td> 194K
代理商： XRT81L27IV
á
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
F
EATURES
................................................................................................................................................... 1
A
PPLICATIONS
.............................................................................................................................................. 1
Figure 1. Block Diagram ................................................................................................................... 1
Figure 2. Pin Out of the XRT81L27 ................................................................................................... 2
ORDERING INFORMATION ............................................................................................................... 2
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTIONS ........................................................................................................... 3
T
ABLE
1: P
IN
N
UMBER
BY
P
IN
N
AME
..................................................................................................... 9
ELECTRICAL CHARACTERISTICS ................................................................................. 10
T
ABLE
2: A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................. 10
T
ABLE
3: DC E
LECTRICAL
C
HARACTERISTICS
..................................................................................... 10
T
ABLE
4: T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
...................................................................... 10
T
ABLE
5: P
ER
C
HANNEL
P
OWER
C
ONSUMPTION
INCLUDING
LINE
POWER
DISSIPATION
,
TRANSMISSION
AND
RECEIVE
PATHS
ALL
ACTIVE
.................................................................................................... 11
T
ABLE
6: R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
........................................................................... 11
Figure 3. Receive Output Timing ................................................................................................... 12
Figure 4. Transmit Input Timing ..................................................................................................... 12
T
ABLE
7: AC E
LECTRICAL
C
HARACTERISTICS
..................................................................................... 12
T
HE
H
ARDWARE
MODE
............................................................................................................................... 13
T
HE
H
OST
M
ODE
....................................................................................................................................... 13
1.0 The Microprocessor Serial Interface (MSI) ........................................................................................... 13
1.1 M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
DESCRIPTION
. ............................................................................ 13
U
SING
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
(MSI) ............................................................................ 13
1.1.1 Selection Phase ........................................................................................................................ 13
1.1.2 Data phase of the (MSI) operation ........................................................................................... 14
Figure 5. Timing Diagram for the Microprocessor Serial Interface ............................................ 14
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMING
(
SEE
F
IGURE
5) ............................................. 15
Figure 6. Microprocessor Serial Interface Data Structure ........................................................... 15
1.2 D
ESCRIPTION
OF
THE
C
OMMAND
R
EGISTERS
........................................................................................ 16
T
ABLE
9: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
AND
C
ONTROL
........................................................ 16
T
ABLE
10: C
OMMAND
C
ONTROL
R
EGISTER
- A
DDRESS
0000 - HEX 0
X
00 ........................................... 16
(C
OMMON
TO
ALL
S
EVEN
C
HANNELS
) ............................................................................................ 16
T
ABLE
11: L
OCAL
L
OOP
-
BACK
R
EGISTERS
- A
DDRESS
: 0001, HEX 0
X
01 ........................................... 17
T
ABLE
12: R
EMOTE
L
OOP
-
BACK
R
EGISTERS
- A
DDRESS
: 0010, HEX 0
X
02 ......................................... 17
T
ABLE
13: A
NALOG
L
OOP
-
BACK
R
EGISTERS
- A
DDRESS
: 0011, HEX 0
X
03 ......................................... 17
T
ABLE
14: TAOS R
EGISTERS
- A
DDRESS
: 0100, HEX 0
X
04 ............................................................... 17
T
ABLE
15: RAOS R
EGISTERS
- A
DDRESS
: 0101, HEX 0
X
05 ............................................................... 17
T
ABLE
16: PDT
X
R
EGISTERS
- A
DDRESS
: 0110, HEX 0
X
06 ................................................................ 18
1.3 O
PERATION
OF
THE
C
OMMAND
C
ONTROL
R
EGISTER
BITS
(A
DDRESS
: 0000, HEX 0
X
00) ........................ 18
TC
LK
P (
BIT
0) ............................................................................................................................................ 18
RC
LK
P (
BIT
1) ........................................................................................................................................... 18
CODE (
BIT
2) ............................................................................................................................................ 18
SR/DR (
BIT
3) ........................................................................................................................................... 18
MUTE (
BIT
4) ............................................................................................................................................ 18
EXLOS (
BIT
5) .......................................................................................................................................... 18
ARAOS (
BIT
6) .......................................................................................................................................... 18
1.4 C
HANNEL
C
ONTROL
R
EGISTERS
........................................................................................................... 18
LLB[6:0] (
ADDRESS
0001) ......................................................................................................................... 18
RLB[6:0] (
ADDRESS
0010) ......................................................................................................................... 18
ALB
X
(
ADDRESS
0011) .............................................................................................................................. 18
TAOS[6:0] (
ADDRESS
0100) ...................................................................................................................... 18
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