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參數(shù)資料
| 型號： | XRT81L27IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 4/30頁 |
| 文件大?。?/td> | 194K |
| 代理商： | XRT81L27IV |
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XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
á
II
RAOS[6:0] (
ADDRESS
0101) ...................................................................................................................... 18
PDTX[6:0] (
ADDRESS
0110) ....................................................................................................................... 18
2.0 The transmit section ............................................................................................................................... 19
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
. ............................................................................................................... 19
Figure 7. The Interface for the Transmission of Data From the Transmitting Terminal Equipment
to the Transmit Section of the XRT81L27 ......................................................................... 19
2.1.1 Dual-rail input mode .................................................................................................................. 19
Figure 8. Dual Rail Data from the Terminal .................................................................................... 19
2.1.2 Single-rail input mode ............................................................................................................... 19
Figure 9. Single-Rail Data From the Terminal ............................................................................... 20
2.1.3 TClk input .................................................................................................................................. 20
2.2 T
HE
E
NCODER
BLOCK
........................................................................................................................... 20
2.2.1 HDB3 Encoding ......................................................................................................................... 20
Figure 10. HDB3 Encoding .............................................................................................................. 20
2.3 T
HE
MUX
BLOCK
.................................................................................................................................. 20
2.3.1 Timing Control Block ................................................................................................................. 21
2.3.2 The Transmit Clock Duty Cycle Adjust Circuit .......................................................................... 21
2.3.3 Transmit All Ones ...................................................................................................................... 21
2.4 T
HE
P
ULSE
S
HAPING
C
IRCUIT
............................................................................................................... 21
Figure 11. ITU-T G.703 Pulse Template .......................................................................................... 22
2.5 T
HE
L
INE
D
RIVER
BLOCK
...................................................................................................................... 22
2.6 I
NTERFACING
THE
T
RANSMIT
S
ECTIONS
OF
THE
XRT81L27
TO
THE
L
INE
............................................... 22
Figure 12. Illustration of how to interface the Transmit Sections of the XRT81L27 to the Line (for
75 or 120W Applications) ................................................................................................... 23
3.0 The Receive Section ............................................................................................................................... 23
3.1 I
NTERFACING
THE
R
ECEIVE
S
ECTIONS
TO
THE
L
INE
............................................................................... 23
Figure 13. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 75W
(Transformer-Coupled) Applications ................................................................................ 24
Figure 14. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 120W
(Transformer-Coupled) Applications ................................................................................ 24
3.2 C
APACITIVE
-C
OUPLING
THE
R
ECEIVER
TO
THE
L
INE
............................................................................... 25
Figure 15. Capacitive - Coupled Receive Sections of the XRT81L27 to the Line (for Balanced
120W Applications) ............................................................................................................. 25
3.3 T
HE
R
ECEIVE
E
QUALIZER
B
OCK
............................................................................................................ 25
3.4 T
HE
P
EAK
D
ETECTOR
AND
S
LICER
B
LOCK
............................................................................................. 26
3.5 T
HE
LOS D
ETECTOR
BLOCK
................................................................................................................. 26
Figure 16. Package Outline Drawing .............................................................................................. 27
R
EVISIONS
................................................................................................................................................. 28
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| XRT82L34 | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT81L27IV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XR-T8205CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telephone Ringer |
| XR-T8205P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telephone Ringer |
| XRT82D20 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL E1 LINE INTERFACE UNIT |
| XRT82D20_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL E1 LINE INTERFACE UNIT |
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