參數(shù)資料
型號(hào): XRT83SL314IB-L
廠商: Exar Corporation
文件頁(yè)數(shù): 18/83頁(yè)
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 14CH 304TBGA
標(biāo)準(zhǔn)包裝: 27
類(lèi)型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 14/14
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 304-LBGA
供應(yīng)商設(shè)備封裝: 304-TBGA(31x31)
包裝: 托盤(pán)
xr
XRT83SL314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
22
2.6.2
Interference Margin
The interference margin for the XRT83SL314 will be added when the first revision of silicon arrives. The test
configuration for measuring the interference margin is shown in Figure 12.
FIGURE 12. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN
2.6.3
General Alarm Detection and Interrupt Generation
The receive path detects EQFLAG, RLOS, AIS, QRPD, NCLD, and FLS. These alarms can be individually
masked to prevent the alarm from triggering an interrupt. To enable interrupt generation, the Global Interrupt
Enable (GIE) bit must be set "High" in the appropriate global register. Any time a change in status occurs (it
the alarms are enabled), the interrupt pin will pull "Low" to indicate an alarm has occurred. Once the status
registers have been read, the INT pin will return "High". The status registers are Reset Upon Read (RUR).
The interrupts are categorized in a hierarchical process block. Figure 13 is a simplified block diagram of the
interrupt generation process.
FIGURE 13. INTERRUPT GENERATION PROCESS BLOCK
NOTE: The interrupt pin is internally pulled "High" with a 50K
resistor.
2.6.3.1
RLOS (Receiver Loss of Signal)
Sinewave
Generator
Flat Loss
W&G ANT20
Network
Analyzer
Cable Loss
XRT83SL314
14-Channel LIU
E1 = 1,024kHz
T1 = 772kHz
E1 = PRBS 215 - 1
T1 = PRBS 223 - 1
Tx
Rx
External Loopback
Global Interrupt
Enable (GIE="1")
Global Channel Interrupt Status
(Indicates Which Channel(s) Experienced a Change in
Status)
Individual Alarm Status Change
(Indicates Which Alarm Experienced a Change)
Individual Alarm Indication
(Indicates the Alarm Condition Active/Inactive)
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