TABLE 32" />
參數(shù)資料
型號: XRT83SL314IB-L
廠商: Exar Corporation
文件頁數(shù): 60/83頁
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 14CH 304TBGA
標(biāo)準(zhǔn)包裝: 27
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 14/14
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 304-LBGA
供應(yīng)商設(shè)備封裝: 304-TBGA(31x31)
包裝: 托盤
xr
XRT83SL314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
60
TABLE 32: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION
CHANNEL 0-13 (0X07H-0XD7H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used.
D6
FLSDET
FIFO LIMIT STATUS DETECT
The FLSDET is used to determine whether the receiver or trans-
mitter FIFO has reached its limit status. If both FIFOs reach their
limit capacity, this bit will be set to "1".
0 = Receive JA
1 = Transmit JA
RO
0
D5
D4
D3
D2
D1
D0
CLOS5
CLOS4
CLOS3
CLOS2
CLOS1
CLOS0
Cable Loss Indication
This 6-Bit binary word indicates the cable attenuation on the
receiver inputs RTIP/RRING within ±1dB with Bit 5 being the MSB.
RO
0
TABLE 33: MICROPROCESSOR REGISTER 0X08H BIT DESCRIPTION
CHANNEL 0-13 (0X08H-0XD8H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
0
D6
D5
D4
D3
D2
D1
D0
1SEG6
1SEG5
1SEG4
1SEG3
1SEG2
1SEG1
1SEG0
Arbitrary Pulse Generation
The transmit output pulse is divided into 8 individual segments.
This register is used to program the first segment which corre-
sponds to the overshoot of the pulse amplitude. There are four
segments for the top portion of the pulse and four segments for the
bottom portion of the pulse. Segment number 5 corresponds to
the undershoot of the pulse. The MSB of each segment is the sign
bit.
Bit 6 = 0 = Negative Direction
Bit 6 = 1 = Positive Direction
R/W
0
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