參數(shù)資料
型號： XRT83SL314IB-L
廠商： Exar Corporation
文件頁數(shù)： 58/83頁
文件大小： 0K
描述： IC LIU SH T1/E1/J1 14CH 304TBGA
標準包裝： 27
類型： 線路接口裝置（LIU）
驅動器/接收器數(shù)： 14/14
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 304-LBGA
供應商設備封裝： 304-TBGA（31x31）
包裝： 托盤
xr
XRT83SL314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
58
D4
LCV/OF
Line Code Violation / Counter Overflow
This bit serves a dual purpose. By default, this bit monitors the line
code violation activity. However, if bit 7 in register 0xE5h is set to a
"1", this bit monitors the overflow status of the internal LCV
counter. An interrupt will not occur unless the LCV/OFIE is set to
"1" in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = A line code violation, bipolar violation, or excessive zeros has
occurred
RO
0
D3
NLCD
Network Loop Code Detection
The network loop code detection is always active regardless if the
interrupt generation is disabled. This bit indicates the NLCD activ-
ity. An interrupt will not occur unless the NLCDIE is set to "1" in the
channel register 0x04h and GIE is set to "1" in the global register
0xE0h.
0 = No Alarm
1 = Network loop code detected according to the mode selected in
channel register 0x03h
RO
0
D2
AISD
Alarm Indication Signal
The alarm indication signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the AIS
activity. An interrupt will not occur unless the AISIE is set to "1" in
the channel register 0x04h and GIE is set to "1" in the global regis-
ter 0xE0h.
0 = No Alarm
1 = An all ones signal is detected
RO
0
D1
RLOS
Receiver Loss of Signal
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = An RLOS condition is present
RO
0
D0
QRPD
Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0x04h and GIE is set to "1" in
the global register 0xE0h.
0 = No Alarm
1 = A QRP is detected
RO
0
NOTE: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
TABLE 30: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
CHANNEL 0-13 (0X05H-0XD5H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
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