xr
XRT83SL314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
50
TABLE 21: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0])
REGISTER
NUMBER
ADDRESS (HEX)
FUNCTION
0 - 15
0x00 - 0x0F
Channel 0 Control Registers
16 - 31
0x10 - 0x1F
Channel 1 Control Registers
32 - 47
0x20 - 0x2F
Channel 2 Control Registers
48 - 63
0x30 - 0x3F
Channel 3 Control Registers
64 - 79
0x40 - 0x4F
Channel 4 Control Registers
80 - 95
0x50 - 0x5F
Channel 5 Control Registers
96 - 111
0x60 - 0x6F
Channel 6 Control Registers
112 - 127
0x70 - 0x7F
Channel 7 Control Registers
128 - 143
0x80 - 0x8F
Channel 8 Control Registers
144 - 159
0x90 - 0x9F
Channel 9 Control Registers
160 - 175
0xA0 - 0xAF
Channel 10 Control Registers
176 - 191
0xB0 - 0xBF
Channel 11 Control Registers
192 - 207
0xC0 - 0xCF
Channel 12 Control Registers
208 - 223
0xD0 - 0xDF
Channel 13 Control Registers
224 - 227
0xE0 - 0xEB
Global Control Registers Applied to All 14 Channels
228 - 243
0xEC - 0xF3
R/W Registers Reserved for Testing
244
0xF4
E1 Arbitrary Select
245 - 253
0xF5 - 0xFD
R/W Registers Reserved for Testing
254
0xFE
Device "ID"
255
0xFF
Device "Revision ID"
TABLE 22: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION
REG
ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
Channel 0 Control Registers (0x00 - 0x0F)
0
0x00
R/W
QRSS/PRBS
Reserved
RxON
EQC4
EQC3
EQC2
EQC1
EQC0
1
0x01
R/W
RxTSEL
TxTSEL
TERSEL1
TERSEL0
RxJASEL
TxJASEL
JABW
FIFOS
2
0x02
R/W
INVQRSS
TxTEST2
TxTEST1
TxTEST0
TxON
LOOP2
LOOP1
LOOP0
3
0x03
R/W
NLCDE1
NLCDE0
CODES
RxRES1
RxRES0
INSBPV
INSBER
Reserved
4
0x04
R/W
EQFLAGE
DMOIE
FLSIE
LCVI/OFE
NLCDIE
AISDIE
RLOSIE
QRPDIE
5
0x05
RO
EQFLAG
DMO
FLS
LCV/OF
NLCD
AIS
RLOS
QRPD
6
0x06
RUR
EQFLAGS
DMOIS
FLSIS
LCV/OFIS
NLCDIS
AISIS
RLOSIS
QRPDIS