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XRT83SL314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
68
TABLE 48: MICROPROCESSOR REGISTER 0XE7H BIT DESCRIPTION
D2
BYTEsel
LCV Counter Byte Select
This bit is used to select the MSB or LSB for Reading the contents
of the LCV counter for a given channel. The channel is addressed
by using bits D[3:0] in register 0xE5h. By default, the LSB byte is
selected.
0 = Low Byte
1 = High Byte
R/W
0
D1
chUPDATE LCV Counter Update Per Channel
This bit is used to latch the contents of the counter for a given
channel into a holding register so that the value of the counter can
be read. The channel is addressed by using bits D[3:0] in register
0xE5h.
0 = Normal Operation
1 = Updates the Selected Channel
R/W
0
D0
Reserved
LCV Counter Reset Per Channel
This bit is used to reset the LCV counter of a given channel to its
default state 0000h. The channel is addressed by using bits D[3:0]
in register 0xE5h. This bit must be set to "1" for 1
S.
0 = Normal Operation
1 = Resets the Selected Channel
R/W
0
GLOBAL REGISTER (0XE7H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
R/W
0
D6
Reserved
This Register Bit is Not Used
R/W
0
D5
Reserved
This Register Bit is Not Used
R/W
0
D4
Reserved
This Register Bit is Not Used
R/W
0
D3
Reserved
This Register Bit is Not Used
R/W
0
D2
Reserved
This Register Bit is Not Used
R/W
0
D1
Reserved
This Register Bit is Not Used
R/W
0
D0
Reserved
This Register Bit is Not Used
R/W
0
GLOBAL REGISTER (0XE6H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)