參數(shù)資料
型號: XRT86VL32_2
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 102/155頁
文件大?。?/td> 814K
代理商: XRT86VL32_2
XRT86VL32
97
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
1
SE_ENB
R/W
0
Synchronization Bit (CRC-6) Error Interrupt Enable
This bit permits the user to either enable or disable the “CRC-6 Error
Detection” Interrupt, within the XRT86VL32 device. If the user enables
this interrupt, then the Receive T1 Framer block will generate an inter-
rupt when it detects a CRC-6 error within the incoming T1 multiframe.
0 - Disables the “CRC-6 Error Detection” Interrupt.
1 - Enables the “CRC-6 Error Detection” Interrupt.
0
FE_ENB
R/W
0
Framing Bit Error Interrupt Enable
This bit permits the user to either enable or disable the “Framing Align-
ment Bit Error Detection” Interrupt, within the XRT86VL32 device. If the
user enables this interrupt, then the Receive T1 Framer block will gen-
erate an interrupt when it detects one or more Framing Alignment Bit
error within the incoming T1 data stream.
0 - Disables the “Framing Alignment Bit Error Detection” Interrupt.
1 - Enables the “Framing Alignment Bit Error Detection” Interrupt.
N
OTE
:
Detecting Framing Alignment Bit Error doesn't not necessarily
indicate that synchronization has been lost.
T
ABLE
83: F
RAMER
I
NTERRUPT
E
NABLE
R
EGISTER
(FIER) H
EX
A
DDRESS
: 0
X
nB05
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
相關(guān)PDF資料
PDF描述
XRT86VL32 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT86VL34 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
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