參數(shù)資料
型號: XRT86VL32_2
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 123/155頁
文件大?。?/td> 814K
代理商: XRT86VL32_2
XRT86VL32
118
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3
RxEOT
RUR/
WC
0
Receive HDLC3 Controller End of Reception (RxEOT) Interrupt
Status
This Reset-Upon-Read bit indicates whether or not the Receive
HDLC3 Controller End of Reception (RxEOT) Interrupt has occurred
since the last read of this register. Receive HDLC3 Controller will
declare this interrupt once it has completely received a full data link
message, or once the buffer is full.
0 = Receive HDLC3 Controller End of Reception (RxEOT) interrupt has
not occurred since the last read of this register
1 = Receive HDLC3 Controller End of Reception (RxEOT) Interrupt has
occurred since the last read of this register
2
FCS Error
RUR/
WC
0
FCS Error Interrupt Status
This Reset-Upon-Read bit indicates whether or not the FCS Error Inter-
rupt has occurred since the last read of this register. Receive HDLC3
Controller will declare this interrupt when it has detected the FCS error
in the most recently received data link message.
0 = FCS Error interrupt has not occurred since the last read of this reg-
ister
1 = FCS Error interrupt has occurred since the last read of this register
1
Rx ABORT
RUR/
WC
0
Receipt of Abort Sequence Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Receipt of Abort
Sequence interrupt has occurred since last read of this register.
Receive HDLC3 Controller will declare this interrupt if it detects the
Abort Sequence (i.e. a string of seven (7) consecutive 1’s) in the
incoming data link channel.
0 = Receipt of Abort Sequence interrupt has not occurred since last
read of this register
1 = Receipt of Abort Sequence interrupt has occurred since last read of
this register
0
RxIDLE
RUR/
WC
0
Receipt of Idle Sequence Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Receipt of Idle
Sequence interrupt has occurred since the last read of this register.
The Receive HDLC3 Controller will declare this interrupt if it detects the
flag sequence octet (0x7E) in the incoming data link channel. If RxI-
DLE "AND" RxEOT occur together, then the entire HDLC message has
been received.
0 = Receipt of Idle Sequence interrupt has not occurred since last read
of this register
1 = Receipt of Idle Sequence interrupt has occurred since last read of
this register.
T
ABLE
100: D
ATA
L
INK
S
TATUS
R
EGISTER
3 (DLSR3) H
EX
A
DDRESS
: 0
XN
B26
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
相關(guān)PDF資料
PDF描述
XRT86VL32 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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