參數(shù)資料
型號(hào): XRT86VL32_2
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 117/155頁
文件大?。?/td> 814K
代理商: XRT86VL32_2
XRT86VL32
112
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
T
ABLE
96: D
ATA
L
INK
S
TATUS
R
EGISTER
2 (DLSR2) H
EX
A
DDRESS
: 0
X
nB16
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
MSG TYPE
RO
0
HDLC2 Message Type Identifier
This READ ONLY bit indicates the type of data link message
received by Receive HDLC 2 Controller. Two types of data link mes-
sages are supported within the XRT86VL32 device: Message Ori-
ented Signaling (MOS) or Bit-Oriented Signalling (BOS).
0 = Indicates Bit-Oriented Signaling (BOS) type data link message is
received
1 = Indicates Message Oriented Signaling (MOS) type data link
message is received
6
TxSOT
RUR/
WC
0
Transmit HDLC2 Controller Start of Transmission (TxSOT)
Interrupt Status
This Reset-Upon-Read bit indicates whether or not the “Transmit
HDLC2 Controller Start of Transmission (TxSOT) “Interrupt has
occurred since the last read of this register. Transmit HDLC2 Con-
troller will declare this interrupt when it has started to transmit a data
link message. For sending large HDLC messages, start loading the
next available buffer once this interrupt is detected.
0 = Transmit HDLC2 Controller Start of Transmission (TxSOT) inter-
rupt has not occurred since the last read of this register
1 = Transmit HDLC2 Controller Start of Transmission interrupt
(TxSOT) has occurred since the last read of this register.
5
RxSOT
RUR/
WC
0
Receive HDLC2 Controller Start of Reception (RxSOT) Interrupt
Status
This Reset-Upon-Read bit indicates whether or not the Receive
HDLC2 Controller Start of Reception (RxSOT) interrupt has
occurred since the last read of this register. Receive HDLC2 Con-
troller will declare this interrupt when it has started to receive a data
link message.
0 = Receive HDLC2 Controller Start of Reception (RxSOT) interrupt
has not occurred since the last read of this register
1 = Receive HDLC2 Controller Start of Reception (RxSOT) interrupt
has occurred since the last read of this register
4
TxEOT
RUR/
WC
0
Transmit HDLC2 Controller End of Transmission (TxEOT) Inter-
rupt Status
This Reset-Upon-Read bit indicates whether or not the Transmit
HDLC2 Controller End of Transmission (TxEOT) Interrupt has
occurred since the last read of this register. Transmit HDLC2 Con-
troller will declare this interrupt when it has completed its transmis-
sion of a data link message. For sending large HDLC messages, it
is critical to load the next available buffer before this interrupt
occurs.
0 = Transmit HDLC2 Controller End of Transmission (TxEOT) inter-
rupt has not occurred since the last read of this register
1 = Transmit HDLC2 Controller End of Transmission (TxEOT) inter-
rupt has occurred since the last read of this register
相關(guān)PDF資料
PDF描述
XRT86VL32 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL32_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL32IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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