參數(shù)資料
型號: XRT86VL32_2
廠商: Exar Corporation
元件分類: 通信及網絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 41/155頁
文件大小: 814K
代理商: XRT86VL32_2
XRT86VL32
36
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
T
ABLE
22: DMA 1 (R
EAD
) C
ONFIGURATION
R
EGISTER
(D1RCR) H
EX
A
DDRESS
: 0
X
n119
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-6
Reserved
-
-
Reserved
7
DMA1 RST
R/W
0
DMA_1 Reset
This bit resets the Receive DMA (Read) Channel 1
0 = Normal operation.
1 = A zero to one transition resets the Receive DMA (Read) channel 1.
6
DMA1 ENB
R/W
0
DMA1_ENB
This bit enables the Receive DMA_1 (Read) interface. After a receive
DMA is enabled, DMA transfers are only requested when the receive
cell buffer contains a complete message or cell.
The DMA read channel is used by the T1 Framer to transfer data from
the HDLC buffers within the T1 Framer to external memory. The DMA
Read cycle starts by T1 Framer asserting the DMA Request (REQ1)
‘low’, then the external DMA controller should drive the DMA Acknowl-
edge (ACK1) ‘low’ to indicate that it is ready to receive the data. The
T1 Framer should place new data on the Microprocessor data bus
each time the Read Signal is Strobed low if the RD is configured as a
Read Strobe. If RD is configured as a direction signal, then the T1
Framer would place new data on the Microprocessor data bus each
time the Write Signal (WR) is Strobed low.
0 = Disables the DMA_1 (Read) interface
1 = Enables the DMA_1 (Read) interface
5
RD TYPE
R/W
0
READ Type Select
This bit selects the function of the RD signal.
0 = RD functions as a Read Strobe signal
1 = RD acts as a direction signal (indicates whether the current bus
cycle is a read or write operation), and WR works as a data strobe.
4 - 3 Reserved
-
-
Reserved
2
DMA1_CHAN(2)
R/W
0
Channel Select
These three bits select which T1 channel within the chip uses the
Receive DMA_1 (Read) interface.
000 = Channel 0
001 = Reserved
001 = Channel 2
011 = Reserved
1xx = Reserved
1
DMA1_CHAN(1)
R/W
0
0
DMA1_CHAN(0)
R/W
0
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