參數(shù)資料
型號： XRT86VL34_2
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 34/156頁
文件大?。?/td> 816K
代理商： XRT86VL34_2
XRT86VL34
29
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
15: R
ECEIVE
I
N
F
RAME
R
EGISTER
(RIFR) H
EX
A
DDRESS
: 0
X
n112
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
In Frame
RO
0
In Frame State
This READ-ONLY bit indicates whether the Receive T1 Framer block is
currently declaring the “In-Frame” condition with the incoming T1 data-
stream.
0 - Indicates that the Receive T1 Framer block is currently declaring the
LOF (Loss of Frame) Defect condition.
1 - Indicates that the Receive T1 Framer block is currently declaring itself
to be in the “In-Frame” condition.
6-0
Reserved
-
-
Reserved (E1 Mode Only)
T
ABLE
16: D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR1) H
EX
A
DDRESS
: 0
X
n113
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
SLC-96 Data Link
Enable
R/W
0
SLC96 DataLink Enable
This bit permits the user to configure the channel to support the
transmission and reception of the “SLC-96 type” of data-link mes-
sage.
0 - Channel does not support the transmission and reception of
“SLC-96” type of data-link messages. Regular SF framing bits will
be transmitted.
1 - Channel supports the transmission and reception of the “SLC-
96” type of data-link messages.
This bit is only active if the channel has been configured to operate
in either the SLC-96 or the ESF Framing formats.
6
MOS ABORT Disable
R/W
0
MOS ABORT Disable:
This bit permits the user to either enable or disable the “Automatic
MOS ABORT” feature within Transmit HDLC Controller # 1. If the
user enables this feature, then Transmit HDLC Controller block # 1
will automatically transmit the ABORT Sequence (e.g., a zero fol-
lowed by a string of 7 consecutive “1s”) whenever it abruptly transi-
tions from transmitting a MOS type of message, to transmitting a
BOS type of message.
If the user disables this feature, then the Transmit HDLC Controller
Block # 1 will NOT transmit the ABORT sequence, whenever it
abruptly transitions from transmitting a MOS-type of message to
transmitting a BOS-type of message.
0 - Enables the “Automatic MOS Abort” feature
1 - Disables the “Automatic MOS Abort” feature
5
Rx_FCS_DIS
R/W
0
Receive Frame Check Sequence (FCS) Verification Enable/Dis-
able
This bit permits the user to configure the Receive HDLC Controller
Block # 1 to compute and verify the FCS value within each incoming
LAPD message frame.
0 - Enables FCS Verification
1 - Disables FCS Verification
相關(guān)PDF資料
PDF描述
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB484 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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XRT86VL34IB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
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