參數(shù)資料
型號(hào)： XRT86VL34_2
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 39/156頁
文件大小： 816K
代理商： XRT86VL34_2
XRT86VL34
34
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
T
ABLE
19: S
LIP
B
UFFER
C
ONTROL
R
EGISTER
(SBCR) H
EX
A
DDRESS
: 0
X
n116
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
TxSB_ISFIFO
R/W
0
Transmit Slip Buffer Mode
This bit permits the user to configure the Transmit Slip Buffer to function as
either “Slip-Buffer” Mode, or as a “FIFO”, as depicted below.
0 - Configures the Transmit Slip Buffer to function as a “Slip-Buffer”.
1 - Configures the Transmit Slip Buffer to function as a “FIFO”.
N
OTE
:
Transmit slip buffer is only used in high-speed or multiplexed mode
where TxSERCLKn must be configured as inputs only. Users must
make sure that the “Transmit Direction” timing (i.e. TxMSYNC) and
the TxSerClk input clock signal are synchronous to prevent any
transmit slips from occuring.
N
OTE
:
The data latency is dictated by FIFO Latency in the FIFO Latency
Register (register 0xn117).
6-5
Reserved
-
-
Reserved
4
SB_FORCESF
R/W
0
Force Signaling Freeze
This bit permits the user to freeze any signaling update on the RxSIGn output
pin as well as the Receive Signaling Array Register -RSAR (0xn500-0xn51F)
until this bit is cleared.
0 = Signaling on RxSIG and RSAR is updated immediately.
1 = Signaling on RxSIG and RSAR is not updated until this bit is set to ‘0’.
3
SB_SFENB
R/W
0
Signal Freeze Enable Upon Buffer Slips
This bit enables signaling freeze for one multiframe after the receive buffer
slips.
If signaling freeze is enabled, then the “Receive Channel” will freeze all sig-
naling updates on RxSIG pin and RSAR (0xn500-0xn51F) for at least “one-
multiframe” period, after a “slip-event” has been detected within the “Receive
Slip Buffer”.
0 = Disables signaling freeze for one multi-frame after receive buffer slips.
1 = Enables signaling freeze for one multi-frame after receive buffer slips.
2
SB_SDIR
R/W
1
Slip Buffer (RxSync) Direction Select
This bit permits user to select the direction of the receive frame boundary
(RxSYNC) signal if the receive buffer is enabled. (i.e. SB_ENB[1:0] = 01 or
10). If slip buffer is bypassed, RxSYNC is always an output pin.
0 = Selects the RxSync signal as an output
1 = Selects the RxSync signal as an input
相關(guān)PDF資料
PDF描述
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL34ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4 IND FULL DPLX FIFO TWO-FRAME, CAS, CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34IB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
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