參數(shù)資料
型號(hào): XRT86VL34_2
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 55/156頁
文件大小: 816K
代理商: XRT86VL34_2
XRT86VL34
50
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1-0
RxIMODE[1:0]
R/W
00
Receive Interface Mode Selection[1:0]
This bit determines the receive backplane interface speed. The exact func-
tion of these two bits depends on whether Receive Multiplexed mode is
enabled or disabled. Table 33 and Table 34 shows the functions of these two
bits for non-multiplexed and multiplexed modes.:
T
ABLE
32: R
ECEIVE
I
NTERFACE
C
ONTROL
R
EGISTER
(RICR) H
EX
A
DDRESS
: 0
XN
122
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
T
ABLE
33: R
ECEIVE
I
NTERFACE
S
PEED
W
HEN
M
ULTIPLEXED
M
ODE
IS
D
ISABLED
(T
X
MUXEN = 0)
R
X
IMODE[1:0]
R
ECEIVE
I
NTERFACE
S
PEED
00
1.544Mbit/s Base Rate Mode
Receive backplane interface signals include:
RxSERCLK is an input or output clock at 1.544MHz
RxSYNC is an input or output signal which indicates the
receive singe frame boundary
RxSER is the base-rate data output
01
2.048Mbit/s High-Speed MVIP Mode:
Receive backplane interface signals include:
RxSERCLK is an input clock at 2.048MHz
RxSYNC is an input signal which indicates the receive
singe frame boundary
RxSER is the high-speed data output
10
4.096Mbit/s High-Speed Mode:
Receive backplane interface signals include:
RxSERCLK is an input clock at 4.096MHz
RxSYNC is an input signal which indicates the receive
singe frame boundary
RxSER is the high-speed data output
11
8.192Mbit/s High-Speed Mode:
Receive backplane interface signals include:
RxSERCLK is an input clock at 8.192MHz
RxSYNC is an input signal which indicates the receive
singe frame boundary
RxSER is the high-speed data output
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