參數(shù)資料
型號: XRT86VL34
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 25/156頁
文件大小: 816K
代理商: XRT86VL34
XRT86VL34
20
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
T
ABLE
8: S
YNCHRONIZATION
MUX R
EGISTER
(SMR) H
EX
A
DDRESS
: 0
X
n109
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
-
-
Reserved
6
MFRAMEALIGN
R/W
0
Transmit Multiframe Sync Alignment
This bit forces Transmit T1 framer block to align with the backplane
multiframe boundary (TxMSYNC_n).
0 = Do not force the transmit T1 framer block to align with the TxM-
SYNC signal.
1 = Force the transmit T1 framer block to align with the TxMSYNC
signal.
N
OTE
:
This bit is not used in base rate (1.544MHz Clock) mode.
5
MSYNC
R/W
O
Transmit Super Frame Boundary
This bit provides an option to use the transmit single frame boundary
(TxSYNC) as the transmit multi-frame boundary (TxMSYNC) in high
speed or multiplexed modes. In 1.544MHz clock mode (base rate),
the TxMSYNC is used as the transmit superframe boundary, in other
clock modes (i.e. high speed or multiplexed modes), TxMSYNC is
used as an input transmit clock for the backplane interface.
0 = Configures the TxSYNC as a single frame boundary.
1 = Configures the TxSYNC as a superframe boundary (TxMSYNC)
in high-speed or multiplexed mode.
N
OTE
:
This bit is not used in base rate (1.544MHz Clock) mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL34_07 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL34_1 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL34_2 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
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