參數(shù)資料
型號： XRT86VL34
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 91/156頁
文件大?。?/td> 816K
代理商： XRT86VL34
XRT86VL34
86
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
T
ABLE
73: T
RANSMIT
S
LIP
C
OUNTER
(TSC) H
EX
A
DDRESS
: 0
X
n90F
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
TxSLIP[7]
RUR
0
Performance Monitor - Transmit Slip Counter (8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Transmit Slip events have been detected by the T1
Framer since the last read of this register.
N
OTE
:
A slip event is defined as a replication or deletion of a T1
frame by the transmit slip buffer.
6
TxSLIP[6]
RUR
0
5
TxSLIP[5]
RUR
0
4
TxSLIP[4]
RUR
0
3
TxSLIP[3]
RUR
0
2
TxSLIP[2]
RUR
0
1
TxSLIP[1]
RUR
0
0
TxSLIP[0]
RUR
0
T
ABLE
74: E
XCESSIVE
Z
ERO
V
IOLATION
C
OUNTER
MSB (EZVCU) H
EX
A
DDRESS
: 0
X
n910
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
EZVC[15]
RUR
0
Performance Monitor - T1 Excessive Zero Violation 16-Bit
Counter - Upper Byte:
These RESET-upon-READ bits, along with that within the “PMON
T1 Excessive Zero Violation Counter Register LSB” combine to
reflect the cumulative number of instances that the ReceiveT1
Excessive Zero Violation has been detected by the Receive T1
Framer block since the last read of this register.
This register contains the Most Significant byte of this 16-bit of the
Receive T1 Excessive Zero Violation counter.
N
OTE
:
For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
EZVC[14]
RUR
0
5
EZVC[13]
RUR
0
4
EZVC[12]
RUR
0
3
EZVC[11]
RUR
0
2
EZVC[10]
RUR
0
1
EZVC[9]
RUR
0
0
EZVC[8]
RUR
0
T
ABLE
75: E
XCESSIVE
Z
ERO
V
IOLATION
C
OUNTER
LSB (EZVCL) H
EX
A
DDRESS
: 0
X
n911
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
EZVC[7]
RUR
0
Performance Monitor - T1 Excessive Zero Violation 16-Bit
Counter - Lower Byte:
These RESET-upon-READ bits, along with that within the “PMON
T1 Excessive Zero Violation Counter Register MSB” combine to
reflect the cumulative number of instances that the ReceiveT1
Excessive Zero Violation has been detected by the Receive T1
Framer block since the last read of this register.
This register contains the Least Significant byte of this 16-bit of the
Receive T1 Excessive Zero Violation counter.
N
OTE
:
For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
EZVC[6]
RUR
0
5
EZVC[5]
RUR
0
4
EZVC[4]
RUR
0
3
EZVC[3]
RUR
0
2
EZVC[2]
RUR
0
1
EZVC[1]
RUR
0
0
EZVC[0]
RUR
0
相關(guān)PDF資料
PDF描述
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB484 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL34_07 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL34_1 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL34_2 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL34ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4 IND FULL DPLX FIFO TWO-FRAME, CAS, CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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