參數(shù)資料
型號: XRT86VL34
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 36/156頁
文件大小: 816K
代理商: XRT86VL34
XRT86VL34
31
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
1
Tx_FCS_EN
R/W
0
Transmit LAPD Message with Frame Check Sequence (FCS)
This bit permits the user to configure the Transmit HDLC Controller
block # 1 to compute and append FCS octets to the “back-end” of
each outbound MOS data-link message.
0 - Configures the Transmit HDLC Controller block # 1 to NOT com-
pute and append the FCS octets to the back-end of each outbound
MOS data-link message.
1 - Configures the Transmit HDLC Controller block # 1 TO COM-
PUTE and append the FCS octets to the back-end of each outbound
MOS data-link message.
N
OTE
:
This bit is ignored if the transmit HDLC1 controller has been
configured to operate in the BOS mode - bit 0 (MOS/BOS)
within this register is set to 0.
0
MOS/BOS
R/W
0
Message Oriented Signaling/Bit Oriented Signaling Send
This bit permits the user to enable LAPD transmission through
HDLC Controller Block # 1 using either BOS (Bit-Oriented Signaling)
or MOS (Message-Oriented Signaling) frames.
0 - Transmit HDLC Controller block # 1 BOS message Send.
1 - Transmit HDLC Controller block # 1 MOS message Send.
N
OTE
:
This is not an Enable bit. This bit must be set to "0" each time
a BOS is to be sent.
T
ABLE
16: D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR1) H
EX
A
DDRESS
: 0
X
n113
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
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參數(shù)描述
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