16-BIT
參數(shù)資料
型號： XRT91L34IVTR-F
廠商： Exar Corporation
文件頁數(shù)： 18/38頁
文件大?。?/td> 0K
描述： IC MULTIRATE CDR QUAD 128LQFP
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘和數(shù)據(jù)恢復(fù)（CDR），扇出緩沖器（分配），多路復(fù)用器
PLL： 是
主要目的： SONET/SDH，STS，STM
輸入： LVDS，LVPECL
輸出： LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 帶卷 (TR)
XRT91L34
25
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
4.2
16-BIT SERIAL DATA INPUT DESCRITPTION
The serial data input is sampled on the rising edge of SCLK. For read operations, the SDO signal is updated
on the falling edge of SCLK. The serial data must be applied to the serial port LSB first. The 16 bits of serial
data are described below.
4.2.1
R/W (SCLK1)
The first serial bit applied to the device SDI pin determines whether a Read or Write operation is desired. If the
R/W bit is set to “0”, the serial port is configured for a Write operation. If the R/W bit is set to “1”, the serial port
is configured for a Read operation.
4.2.2
A[5:0] (SCLK2 - SCLK7)
The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0
(LSB) must be sent to the SDI pin first followed by A1 and so forth until all 6 address bits have been sampled
by SCLK.
4.2.3
X (Dummy Bit SCLK8)
The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data
if the readback mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold
either “0” or “1” during both Read and Write operations.
4.2.4
D[7:0] (SCLK9 - SCLK16)
The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the ad-
dress bits. D0 (LSB) must be sent to the SDI pin first followed by D1 and so forth until all 8 data bits have been
sampled by SCLK. Once 16 SCLK cycles have been complete, the data is held until CS is pulled “High”
whereby, the serial port latches the data into the selected internal register.
4.3
8-BIT SERIAL DATA OUTPUT DESCRIPTION
When R/W is set to “1” (Read operation) the serial data output is updated on the falling edge of SCLK8 -
SCLK16, D0 (LSB) is provided at the SDO pin on the falling edge of SCLK8, followed by D1 and so forth until
all 8 data bits have been updated after which the SDO output pin returns to a high impedance state until the
next read operation.
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參數(shù)描述
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XRT91L80IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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