參數(shù)資料
型號： XRT91L34IVTR-F
廠商： Exar Corporation
文件頁數(shù)： 8/38頁
文件大?。?/td> 0K
描述： IC MULTIRATE CDR QUAD 128LQFP
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘和數(shù)據(jù)恢復(fù)（CDR），扇出緩沖器（分配），多路復(fù)用器
PLL： 是
主要目的： SONET/SDH，STS，STM
輸入： LVDS，LVPECL
輸出： LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 帶卷 (TR)
XRT91L34
16
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
Jitter specification is defined using a 12kHz to 0.4/1.3/5MHz LP-HP single-pole filter.
1These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUI
rms).
2Required to meet SONET output frequency stability requirements.
2.2.1
Internal Clock and Data Recovery Disable
Optionally, each of the four internal CDR unit can be disabled and powered down when the channel is not in
use. Asserting the CDRDISn pin (where n = channel 0, 1, 2, or 3 ) "High" in Hardware Mode or setting
CDRDISn bit (where n = channel 0, 1, 2, or 3 ) in Host Mode, disables the internal Clock and Data Recovery
unit for that particular channel.
2.3
External Receive Loop Filter Capacitors
For STS12/STM4 and STS3/STM1 operation, use 0.47
F (or greater) non-polarized external loop filter
capacitors to achieve the required receiver jitter performance for each of the channels. For STS1/STM0
operation, use a minimum of 1.0
F non-polarized capacitors. If all 3 data rates STS12/STS3/STS1 are
required in an application, then use 1uF loop filter capacitors. They must be well isolated to prohibit noise
entering the CDR block and should be placed as close to the pins as possible. Figure 6 shows the pin
connections and external loop filter components. These four non-polarized capacitors should be of +/- 10%
tolerance. Use type X7R or X5R capacitors for improved stability over temperature.
TABLE 3: CLOCK AND DATA RECOVERY UNIT PERFORMANCE
NAME
PARAMETER
MIN
TYP
MAX
UNITS
REFDUTY
Reference clock duty cycle
40
60
%
REFTOL
Reference clock frequency tolerance2
-100
+100
ppm
TOLJIT
Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern
0.3
0.4
UI
OCLKDUTY
Clock output duty cycle
45
55
%
FIGURE 6. EXTERNAL LOOP FILTERS
CAP1N
CAP1P
0.47uF
non-polarized
CAP3N
CAP3P
0.47uF
non-polarized
CAP0N
CAP0P
0.47uF
non-polarized
Channel 0 Loop Filter
External Capacitor
pin 108
pin 109
pin 103
pin 102
Channel 1 Loop Filter
External Capacitor
CAP2N
CAP2P
0.47uF
non-polarized
Channel 2 Loop Filter
External Capacitor
pin 60
pin 59
pin 53
Pin 54
Channel 3 Loop Filter
External Capacitor
Use 1.
....
0uF non-polarized
capacitors for
STS1/STM0 Operation
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