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參數(shù)資料
型號(hào): XRT91L34IVTR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 20/38頁(yè)
文件大?。?/td> 0K
描述: IC MULTIRATE CDR QUAD 128LQFP
標(biāo)準(zhǔn)包裝: 750
類(lèi)型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: SONET/SDH,STS,STM
輸入: LVDS,LVPECL
輸出: LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 帶卷 (TR)
XRT91L34
27
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
COMMON CONTROL REGISTERS
TABLE 9: MICROPROCESSOR INTERFACE REGISTER 0X00 BIT DESCRIPTION
GLOBAL CONTROL REGISTER (0X00)
BIT
NAME
FUNCTION
Regis-
ter
Type
Default
Value
(HW Reset)
D7
Reserved
This Register Bit is Not Used
RO
0
D6
Reserved
This Register Bit is Not Used
RO
0
D5
Reserved
This Register Bit is Not Used
RO
0
D4
DLOSDIS
DLOS (Digital Loss of Signal) Disable
This global bit is used to disable the channelized internal DLOS
monitoring and automatic muting of RXDO[3:0]P/N recovered data
output pins upon DLOS detection.
"0" = Monitor & Mute recovered data upon LOS declaration
"1" = Disable internal DLOS monitoring
R/W
0
D3
Reserved
This Register Bit is Not Used
RO
0
D2
MINT_EN
Master Interrupt Enable
"0" = Disables Interrupt generation
"1" = Enables Interrupt generation
R/W
0
D1
CDRREFSEL Clock and Data Recovery Unit Reference Frequency Select
This bit is used to select the clock input reference.
"0" = 77.76 MHz reference frequency support
"1" = 19.44 MHz reference frequency support
R/W
0
D0
SWRST
Software Reset
A "0" to "1" transition will asynchronously reset the device and all
register bit settings to their default state. This bit will automatically
reset itself to "0". User does not have to write "0" to this bit to resume
normal operation.
"0" = Normal Operation
"1" = Resets all registers to default values
R/W
0
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