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參數(shù)資料
| 型號： | XRT91L34IVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 7/38頁 |
| 文件大小： | 0K |
| 描述： | IC MULTIRATE CDR QUAD 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），扇出緩沖器（分配），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STS，STM |
| 輸入： | LVDS，LVPECL |
| 輸出： | LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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XRT91L34
15
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
The receive serial inputs can also be AC coupled to an optical module or an electrical interface. A simplified
Differential LVPECL AC coupling using external passive components block diagram is shown in Figure 5.
NOTE: Some optical modules integrate AC coupling capacitors and DC current path resistors internally within the module.
2.2
Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential receiver
and generates a clock that is the same frequency as the incoming data. The clock recovery block utilizes the
reference clock from REFCLKP/N or TTLREFCLK to train and monitor its clock recovery PLL. Upon startup,
the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock onto the
incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local
reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch to the
local reference clock, declare a Loss of Lock and output a high level signal on the LOL output pin. Whenever a
Loss of Lock (LOL) or a Loss of Signal (LOS) event occurs, the CDR will continue to supply a receive clock
(based on the local reference). When the SDEXT becomes active and internal DLOS is cleared and the
recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference source, the
clock recovery PLL will switch back to the incoming receive serial data stream. Table 3 specifies the Clock and
Data Recovery Unit performance characteristics.
FIGURE 5. RECEIVE SERIAL INPUT INTERFACE USING DIFF LVPECL AC COUPLING INTERNAL TERMINATION
Optical Module
RXDI0P
RXDI0N
Optical Fiber
Install DC current path resistors
as close to Optical Module
LVPECL output driver pins
XRT91L34
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
RXDI1P
RXDI1N
RXDI2P
RXDI2N
RXDI3P
RXDI3N
Optical Module
Optical Fiber
Optical Module
Optical Fiber
Optical Module
Optical Fiber
Channel 0
Channel 1
Channel 2
Channel 3
DIFF LVPECL A/C Coupling using
External Passive Components
130 x 8
100
VBB1.2
Internal 100 Ohm line-to-line
termination active on
RXDI[3:0]P and RXDI[3:0]N pins
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L80 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L80_0507 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L80ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L80IB | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L80IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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