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參數(shù)資料
型號(hào): XRT91L34IVTR-F
廠商: Exar Corporation
文件頁數(shù): 3/38頁
文件大?。?/td> 0K
描述: IC MULTIRATE CDR QUAD 128LQFP
標(biāo)準(zhǔn)包裝: 750
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: SONET/SDH,STS,STM
輸入: LVDS,LVPECL
輸出: LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 帶卷 (TR)
XRT91L34
11
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
SERIAL MICROPROCESSOR INTERFACE
NAME
LEVEL
TYPE
PIN
DESCRIPTION
HOST/HW
LVTTL,
LVCMOS
I
122
Host or Hardware Mode Select Input
The XRT91L34 offers two modes of operation for interfacing to the
device. The Host mode uses a serial microprocessor interface for
programming individual registers. The Hardware mode is controlled
by the state of the hardware pins set by the user. When left uncon-
nected, by default, the device is configured in the Hardware mode.
"Low" = Hardware Mode
"High" = Host Mode
This pin is provided with an internal pull-down.
CS
LVTTL,
LVCMOS
I
38
Chip Select Input (Host Mode)
Active "Low" signal. This signal enables the serial microprocessor
interface by pulling chip select "Low". The serial microprocessor is
disabled when the chip select signal returns "High".
NOTES:
1.
The serial microprocessor interface does not support burst
mode. Chip Select must be de-asserted after each
operation cycle.
2.
Chip Select is only active in Host Mode.
This pin is provided with an internal pull-up.
SCLK
LVTTL,
LVCMOS
I
37
Serial Clock Input (Host Mode Only)
Once CS is pulled "Low", the serial microprocessor interface
requires 16 clock cycles for a complete Read or Write operation.
Serial Clock Input is only active in Host Mode.
This pin is provided with an internal pull-down.
DLOSDIS
/SDI
LVTTL,
LVCMOS
I
39
Serial Data Input (Host Mode Only)
When CS is pulled "Low", the serial data input is sampled on the ris-
ing edge of SCLK.
Serial Data Input is only active in Host Mode.
This pin is provided with an internal pull-down.
Hardware Mode This pin is functions as the DLOSDIS control pin.
SDO
LVCMOS
O
40
Serial Data Output (Host Mode Only)
If a Read function is initiated, the serial data output is updated on
the falling edge of SCLK8 through SCLK15, with the LSB (D0)
updated first. This enables the data to be sampled on the rising
edge of SCLK9 through SCLK16.
Serial Data Output is only active in Host Mode.
INT
LVCMOS
O
41
Interrupt Output (Host Mode Only)
Active "Low" signal. This signal is asserted "Low" when a change in
alarm status occurs. Once the status registers have been read, the
interrupt pin will return "High".
Interrupt Output is only active in Host Mode.
NOTE:
This open-drain output pin requires an external pull-up
resistor.
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