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參數(shù)資料
| 型號： | XWM8191CFT |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 14-bit 6MSPS CIS/CCD Analogue Front End/Digitiser |
| 中文描述： | 14位6MSPS獨聯(lián)體/防治荒漠化公約模擬前端/數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大小： | 355K |
| 代理商： | XWM8191CFT |
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Advanced Information
WM8191
WOLFSON MICROELECTRONICS LTD
AI Rev 3.1 April 2001
19
LINE-BY-LINE OPERATION
Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a
full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to
accommodate this type of signal the WM8191 can be set into Monochrome mode, with the input
channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8191
can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is
set the green and blue processing channels are powered down and the device is forced internally to
only operate in MONO mode (because only one colour is sampled at a time) through the red channel.
Figure 19 shows the signal path when operating in colour line-by-line mode.
RINP
SEN/STB
SCK/RNW
VSMP
MCLK
VRLC/VBIAS
SDI/DNA
RLC/ACYC
NRESET
RLC
BINP
GINP
INPUT
MUX
OFFSET
MUX
RLC
R
G
B
R
G
B
PGA
I/P SIGNAL
POLARITY
ADJUST
8
RLC
DAC
+
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
OP[13:0]
+
WM8191
14-
BIT
ADC
DATA
I/O
PORT
8
OFFSET
DAC
PGA
MUX
TIMING CONTROL
CL
V
S
R
S
4
CDS
RLC
Figure 19 Signal Path When in Line-by-Line Mode
In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-
cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.
The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. Alternatively,
all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0]
to select the desired colour. It is also possible for the input multiplexer to be controlled separately
from the PGA and Offset multiplexers. Table 4 describes all the multiplexer selection modes that
are possible.
FME
0
ACYCNRLC
0
NAME
DESCRIPTION
Internal,
no force mux
Auto-cycling,
no force mux
Internal,
force mux
Input mux, offset and gain registers determined by
internal register bits INTM1, INTM0.
Input mux, offset and gain registers auto-cycled, RINP
→
GINP
→
BINP
→
RINP
…
on RLC/ACYC pulse.
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers selected from internal register
bits INTM1, INTM0.
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers auto-cycled, RINP
→
GINP
→
BINP
→
RINP
…
on RLC/ACYC pulse.
0
1
1
0
1
1
Auto-cycling,
force mux
Table 4 Colour Selection Description in Line-by-Line Mode
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