參數(shù)資料
型號: XWM8191CFT
廠商: Wolfson Microelectronics
英文描述: 14-bit 6MSPS CIS/CCD Analogue Front End/Digitiser
中文描述: 14位6MSPS獨聯(lián)體/防治荒漠化公約模擬前端/數(shù)字轉(zhuǎn)換器
文件頁數(shù): 20/27頁
文件大小: 355K
代理商: XWM8191CFT
WM8191
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 3.1 April 2001
20
OPERATING MODES
Table 5 summarises the most commonly used modes, the clock waveforms required and the register
contents required for CDS and non-CDS operation.
MODE
DESCRIPTION
CDS
AVAILABLE
MAX
SAMPLE
RATE
SENSOR
INTERFACE
DESCRIPTION
TIMING
REQUIRE-
MENTS
REGISTER
CONTENTS
WITH CDS
REGISTER
CONTENTS
WITHOUT
CDS
SetReg1:
01(hex)
1
Colour
Pixel-by-Pixel
Yes
2MSPS
The 3 input channels
are sampled in
parallel. The signal is
then gain and offset
adjusted before being
multiplexed into a
single data stream
and converted by the
ADC, giving an output
data rate of 6MSPS
max.
As mode 1 except:
Only one input
channel at a time
is continuously
sampled.
MCLK max
= 12MHz
MCLK:
VSMP
ratio is 6:1
SetReg1:
03(hex)
2
Monochrome/
Colour
Line-by-Line
Yes
2MSPS
MCLK max
= 12MHz
MCLK:
VSMP
ratio is 6:1
MCLK max
= 12MHz
MCLK:
VSMP
ratio is 3:1
SetReg1:
07(hex)
SetReg1:
05(hex)
3
Fast
Monochrome/
Colour
Line-by-Line
Yes
4MSPS
Identical to mode 2
Identical to
mode 2 plus
SetReg3:
bits 5:4 must
be set to
0(hex)
CDS not
possible
Identical to
mode 2
4
Maximum
speed
Monochrome/
Colour
Line-by-Line
No
6MSPS
Identical to mode 2
MCLK max
= 12MHz
MCLK:
VSMP
ratio is 2:1
MCLK max
= 12MHz
MCLK:
VSMP
ratio is
2n:1, n
4
MCLK max
= 12MHz
MCLK:
VSMP
ratio is
2n:1, n
4
SetReg1:
45(hex)
5
Slow Colour
Pixel-by-Pixel
Yes
1.5MSPS
Identical to mode 1
Identical to
mode 1
Identical to
mode 1
6
Slow
Monochrome/
Colour
Line-by-Line
Yes
1.5MSPS
Identical to mode 2
Identical to
mode 2
Identical to
mode 2
Table 5 WM8191 Operating Modes
Notes:
1.
In Monochrome mode, Setup Register 3 bits 7:6 determine which input is to be sampled.
For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection
Description in Line-by-Line Mode.
2.
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