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參數(shù)資料
| 型號： | XWM8191CFT |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 14-bit 6MSPS CIS/CCD Analogue Front End/Digitiser |
| 中文描述： | 14位6MSPS獨聯(lián)體/防治荒漠化公約模擬前端/數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 355K |
| 代理商： | XWM8191CFT |
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WM8191
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 3.1 April 2001
8
OEB
OP[13:0]
t
PZE
Hi-Z
t
PEZ
Hi-Z
Figure 3 Output Data Enable Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = 4.75 to 5.25V, DVDD2 = DVDD3 = 2.97 to 3.63V, AGND = DGND = 0V, T
A
= 0 to 70
°
C,
MCLK = 12MHz unless otherwise stated.
PARAMETER
Output propagation delay
Output enable time
Output disable time
SYMBOL
t
PD
t
PZE
t
PEZ
TEST CONDITIONS
I
OH
= 1mA, I
OL
= 1mA
MIN
TYP
MAX
75
50
25
UNITS
ns
ns
ns
SERIAL INTERFACE
Figure 4 Serial Interface Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = 4.75 to 5.25V, DVDD2 = DVDD3 = 2.97 to 3.63V, AGND = DGND = 0V, T
A
= 0 to 70
°
C,
MCLK = 12MHz unless otherwise stated.
PARAMETER
SCK period
SYMBOL
t
SPER
TEST CONDITIONS
MIN
83.3
TYP
MAX
UNITS
ns
SCK high
t
SCKH
37.5
ns
SCK low
t
SCKL
37.5
ns
SDI set-up time
t
SSU
10
ns
SDI hold time
t
SH
10
ns
SCK to SEN set-up time
t
SCE
20
ns
SEN to SCK set-up time
t
SEC
20
ns
SEN pulse width
t
SEW
50
ns
SEN low to SDO = Register data
t
SERD
35
ns
SCK low to SDO = Register data
t
SCRD
35
ns
SCK low to SDO = ADC data
t
SCADC
25
ns
Note:
Parameters are measured at 50% of the rising/falling edge.
SCK
SDI
SEN
SDO
t
SPER
t
SCKL
t
SCKH
t
SSU
t
SH
t
SCE
t
SEW
t
SEC
t
SERD
t
SCRD
MSB
LSB
t
SCRDZ
ADC DATA
ADC
DATA
REGISTER DATA
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相關代理商/技術參數(shù) |
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|---|---|
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