參數(shù)資料
型號： Z80L182
廠商： ZiLOG, Inc.
英文描述： CAP .0001UF 50V POLYPROPYLENE
中文描述： ZiLOG的智能外設控制器（郵編⑩）
文件頁數(shù)： 9/109頁
文件大?。?/td> 738K
代理商： Z80L182
3-9
Z80182/Z8L182
Z
ILOG
I
NTELLIGENT
P
ERIPHERAL
P R E L I M I N A R Y
Zilog
DS971820600
/W//REQB.
Wait/Request (output, open drain when
programmed for the Wait function, driven High or Low
when programmed for a Request function).This pin is
similar in functionality to /W//REQA but is applicable on
channel B. The /W//REQB signal is multiplexed with the
Z180 MPU CKS signal and the 16550 MIMIC interface
/HTxRDY signal on the CKS//W//REQB//HTxRDY pin.
16550 MIMIC INTERFACE SIGNALS
HD7-HD0.
Host Data Bus (input/output, ri-state). In Z80182/
Z8L182 mode 1, the host data bus is used to communicate
between the 16550 MIMIC interface and the PC/XT/AT. It
is multiplexed with the PA7-PA0 of parallel Port A when the
Z80182/Z8L182 is in mode 0.
/HDDIS.
Host Driver Disable (output, active Low).In Z80182/
Z8L182 mode 1, this signal goes Low whenever the
PC/XT/AT is reading data from the 16550 MIMIC interface.
In Z80182/Z8L182 mode 0, this pin is multiplexed with the
ESCC
TxDB signal on the TxDB//HDDIS pin.
HA2-HA0.
Host Address (input).In Z80182/Z8L182 mode
1, these pins are the address inputs to the 16550 MIMIC
interface. This address determines which register the
PC/XT/AT accesses. HA0 is multiplexed with /TRxCB on
the /TRxCB/HA0 pin; HA1 is multiplexed with RxDB on the
RxDB/HA1 pin; HA2 is multiplexed with /RTxCB on the
/RTxCB/HA2 pin.
/HCS.
Host Chip Select (input, active Low).In Z80182/
Z8L182 mode 1, this input is used by the PC/XT/AT to
select the 16550 MIMIC interface for an access. In Z80182/
Z8L182 mode 0, it is multiplexed with the ESCC /SYNCB
signal on the SYNCB//HCS pin.
/HWR.
Host Write (Input, active Low).In Z80182/Z8L182
mode 1, this input is used by the PC/XT/AT to signal the
16550 MIMIC interface that a write operation is taking
place. In Z80182/Z8L182 mode 0, this input is multiplexed
with the ESCC /CTSB signal on the /CTSB//HWR pin.
/HRD.
Host Read (input, active Low).In Z80182/Z8L182
mode 1, this input is used by the PC/XT/AT to signal the
16550 MIMIC interface that a read operation is taking
place. In Z80182/Z8L182 mode 0, this pin is multiplexed
with the ESCC /DCDB signal on the /DCDB//HRD pin.
HINTR.
Host Interrupt (output, active High).In Z80182/
Z8L182 mode 1, this output is used by the 16550 MIMIC
interface to signal the PC/XT/AT that an interrupt is pending.
In Z80182/Z8L182 mode 0, this pin is multiplexed with the
ESCC (/DTR//REQB) signal and the Z180 MPU TxS signal
on the TxS//DTR//REQB//HINTR pin.
/HTxRDY.
Host Transmit Ready (output, active Low). In
Z80182/Z8L182 mode 1, this output is used by the 16550
MIMIC in DMA mode to signal the PC/XT/AT that the
Transmit Holding Register is empty. In Z80182/Z8L182
mode 0, this pin is multiplexed with the ESCC (/W//REQB)
signal and the Z180 MPU CKS signal on the CKS//W//
REQB//HTxRDY pin.
/HRxRDY.
Host Receive Ready (output, active Low).In
Z80182/Z8L182 mode 1, this output is used by the 16550
MIMIC interface in DMA mode to signal the PC/XT/AT that
a data byte is ready in the Receive Buffer. In Z80182/
Z8L182 mode 0, this pin is multiplexed with the ESCC
/RTSB signal and the Z180 MPU /TEND1 signal on the
/TEND1/RTSB /HRxRDY pin.
PA7-PA0.
Parallel Port A (input/output). These lines can be
configured as inputs or outputs on a bit-by-bit basis when
the Z80182/Z8L182 is operated in mode 0. These pins are
multiplexed with the HD7-HD0 when the Z80182/Z8L182 is
in mode 1.
PB7-PB0.
Parallel Port B (input/output). These lines can be
configured as inputs or outputs on a bit-by-bit basis when
the Port function is selected in the System Configuration
register. The pins are multiplexed with the following Z180
peripheral functions: /RTS0, /CTS0, /DCD0, TxA0, RxA0,
TxA1, RxA1, (RxS//CTS1).
PC7-PC0.
Parallel Port C (input/output). These lines can
be configured as inputs or outputs on a bit-by-bit basis for
bits PC5-PC0. Bits PC7 and PC6 are input only and read
the level of the external /INT2 and /INT1 pins. When /INT2
and/or /INT1 are in edge capture mode, writing a 1 to the
respective PC7, PC6 bit clears the interrupt capture latch;
writing a 0 has no effect. Bits PC5-PC0 are multiplexed with
the following pins from ESCC channel A: (/W//REQA),
/SYNCA, (/DTR//REQA), /RTSA, /MWR, /CTSA, /DCDA.
The Port function is selected through a bit in the System
Configuration Register.
PARALLEL PORTS
相關PDF資料
PDF描述
Z8018533FSC SMART PERIPHERAL CONTROLLERS
Z8019533FSC SMART PERIPHERAL CONTROLLERS
Z80185 SMART PERIPHERAL CONTROLLERS
Z8018520FSC SMART PERIPHERAL CONTROLLERS
Z80195 SMART PERIPHERAL CONTROLLERS
相關代理商/技術參數(shù)
參數(shù)描述
Z80L18320ASC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
Z80L183AZ033SCRXXXX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
Z80PIO 制造商:Zilog Inc 功能描述:
Z80S183 制造商:ZILOG 制造商全稱:ZILOG 功能描述:Family MPU
Z80S18333ASC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*