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3-97
Z80182/Z8L182
Z
ILOG
I
NTELLIGENT
P
ERIPHERAL
P R E L I M I N A R Y
Zilog
DS971820600
Table D. Z85230 System Timing Table
20 MHz
Min
No.
Symbol
Parameter
Max
Notes [4]
1
2
3
4
5
TdRxC(REQ)
TdRxC(W)
TdRxC(SY)
TdRxC(INT)
TdTxC(REQ)
/RxC to /W//REQ Valid
/RxC to /Wait Inactive
/RxC to /SYNC Valid
/RxC to /INT Valid
/TxC to /W//REQ Valid
13
13
9
15
8
18
18
13
22
12
[2]
[1,2]
[2]
[1,2]
[3]
6
7
8
9
10
TdTxC(W)
TdTxC(DRQ)
TdTxC(INT)
TdSY(INT)
TdExT(INT)
/TxC to /Wait Inactive
/TxC to /DTR//REQ Valid
/TxC to /INT Valid
/SYNC to /INT Valid
/DCD or /CTS to /INT Valid
8
7
9
2
3
15
11
14
6
9
[1,3]
[3]
[1,3]
[1]
[1]
Notes:
These AC parameters values are preliminary and subject to change without notice.
[1] Open-drain output, measured with open-drain test load.
[2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[3] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[4] Units equal to TcPc
Table E. I/O Port Timing
Z8L182
20 MHz
Min
Z80182
33 MHz
Min
No.
Symbol
Parameter
Max
Max
1
2
3
4
TsPIA(RD)
ThPIA(RD)
TdWR
F
(PIA)
T
F
WR
F
(PIA)
Port Data Input Setup to /RD Fall
Port Data Input Hold From /RD Rise
Port Data Output Delay From /WR Fall
Port Data Output Float From /WR Fall
20
0
20
0
60
60
0
0
Table F. External Bus Master Timing
Z8L182
20 MHz
Min
Z80182
33 MHz
Min
No.
Symbol
Parameter
Max
Max
1
2
3
4
TsA(IORQf)
TsIOf(WRf)
TsIOf(RDf)
ThIOR(WR
R
)
Address to /IORQ Fall Setup
/IORQ Fall to /WR Fall Setup
/IORQ Fall to /RD Fall Setup
/IORQ Rise From /WR Rise Hold
10
0
0
0
5
0
0
0
5
6
7
8
9
ThIOR(RD
R
)
TdRDf(DO)
T
H
RD
(DO)
T
D(WR
R
)
THD(WR
R
)
/IORQ Rise From /RD Rise Hold
/RD Fall to Data Out Valid Delay
/RD Rise to Data Out Valid Hold
Data In to /WR Fall Setup
Data In From /WR Rise Hold
0
0
50
0
45
0
50
10
50
10
8