參數(shù)資料
型號： Z8S18006PSC
廠商： ZiLOG, Inc.
元件分類： 微處理器
英文描述： CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE
中文描述： 強化Z180微處理器
文件頁數(shù)： 35/70頁
文件大?。?/td> 387K
代理商： Z8S18006PSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-35
1
CPU CONTROL REGISTER
CPU Control Register (CCR).
This register controls the
basic clock rate, certain aspects of Power-Down modes,
and output drive/low noise options (Figure 31).
Bit 7.
Clock Divide Select. If this bit is 0, as it is after a Re-
set, the Z80180/Z8S180/Z8L180 divides the frequency on
the XTAL pin(s) by two to obtain its master clock PHI. If this
bit is programmed as 1, the part uses the XTAL frequency
as PHI without division.
If an external oscillator is used in divide-by-one mode, the
minimum pulse width requirement given in the AC Charac-
teristics must be satisfied.
Bits 6 and 3.
STANDBY/IDLE Control. When these bits
are
both
0,
a
SLP
Z80180/Z8S180/Z8L180 enter SLEEP or SYSTEM STOP
mode, depending on the IOSTOP bit (ICR5).
instruction
makes
the
When D6 is 0 and D3 is 1, setting the IOSTOP bit (ICR5)
and
executing
a
SLP
Z80180/Z8S180/Z8L180 into IDLE mode in which the on-
chip oscillator runs, but its output is blocked from the rest
of the part, including PHI out.
instruction
puts
the
When D6 is 1 and D3 is 0, setting IOSTOP (ICR5) and ex-
ecuting a SLP instruction puts the part into STANDBY
mode, in which the on-chip oscillator is stopped and the
part allows 217 (128K) clock cycles for the oscillator to sta-
bilize when it's restarted.
When D6 and D3 are both 1, setting IOSTOP (ICR5) and
executing a SLP instruction puts the part into QUICK RE-
COVERY STANDBY mode, in which the on-chip oscillator
is stopped, and the part allows only 64 clock cycles for the
oscillator to stabilize when it's restarted.
The latter section, HALT and LoW POWER Modes, de-
scribes the subject more fully.
Bit 5 BREXT.
This bit controls the ability of the
Z8S180/Z8L180 to honor a bus request during STANDBY
mode. If this bit is set to 1 and the part is in STANDBY
mode, a BUSREQ is honored after the clock stabilization
timer is timed out.
Bit 4 LNPHI.
This bit controls the drive capability on the
PHI Clock output. If this bit is set to 1, the PHI Clock output
will be reduced to 33 percent of its drive capability.
Figure 31. CPU Control Register (CCR) Address 1FH
D7
LNAD/DATA
0 = Standard Drive
1 = 33% Drive on
A19-A0, D7-D0
D6 D5 D4 D3 D2 D1 D0
CPU Control Register (CCR)
LNCPUCTL
0 = Standard Drive
1 = 33% Drive on CPU
Control Signals
LNIO
0 = Standard Drive
1 = 33% Drive on
Group 1 I/O Signals
LNPHI
0 = Standard Drive
1 = 33% Drive on
PHI Pin
Clock Divide
0 = XTAL/2
1 = XTAL/1
STANDBY/IDLE Enable
00 = No STANDBY
01 = IDLE After SLEEP
10 = STANDBY After SLEEP
11 = STANDBY After SLEEP
64-Cycle Exit
(QUICK RECOVERY)
BREXT
0 = Ignore BUSREQ
on STANDBY/IDLE
1 = STANDBY/IDLE Exit
on BUSREQ
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