參數(shù)資料
型號: Z8S18006PSC
廠商: ZiLOG, Inc.
元件分類: 微處理器
英文描述: CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE
中文描述: 強化Z180微處理器
文件頁數(shù): 48/70頁
文件大?。?/td> 387K
代理商: Z8S18006PSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-48
P R E L I M I N A R Y
DS971800401
ASCI TIME CONSTANT REGISTERS
If the SS2-0 bits of the CNTLA register are not 111, and the
BRG Mode bit in the ASEXT register is 1, the ASCI divides
the PHI clock by twice (the 16-bit value in these registers,
plus two), to obtain the clock that is presented to the trans-
mitter and receiver for division by 1, 16, or 64 and that can
be output on the CKA1 pin.
Figure 53. ASCI Time Constant Registers
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
ASCI Time Constant Register 0 Low (ASTCOL, I/O Address IAH)
ASCI Time Constant Register 1 Low (ASTCIL), I/O Address ICH)
ASCI Time Constant Register 0 High (ASTCOH, I/O Address IBH)
ASCI Time Constant Register 1 High (ASTCIH), I/O Address IDH)
LS 8 Bits of Time Constant
MS 8 Bits of Time Constant
相關PDF資料
PDF描述
Z90102 CAP 560PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014
Z90103 CAP 680PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014
Z90104 CAP 820PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014
Z90110 CAP 1000PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014
Z90120 CAP 1000PF 100V 20% X7R AXIAL BULK R-MIL-PRF-39014
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