參數(shù)資料
型號： Z8S18006PSC
廠商： ZiLOG, Inc.
元件分類： 微處理器
英文描述： CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE
中文描述： 強化Z180微處理器
文件頁數(shù)： 55/70頁
文件大?。?/td> 387K
代理商： Z8S18006PSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-55
1
DMA STATUS REGISTER (DSTAT)
DSTAT is used to enable and disable DMA transfer and
DMA termination interrupts. DSTAT also indicates DMA
transfer status, in other words, completed or in progress.
Mnemonic DSTAT
Address 30
DE1: DMA Enable Channel 1 (bit 7).
When DE1 = 1 and
DME = 1, channel 1 DMA is enabled. When a DMA trans-
fer terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC.
When DE1 = 0 and the DMA interrupt is enabled (DIE1 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE1, DWE1 should be writ-
ten with 0 during the same register write access. Writing
DE1 to 0 disables channel 1 DMA, but DMA is restartable.
Writing DE1 to 1 enables channel 1 DMA and automatical-
ly sets DME (DMA Main Enable) to 1. DE1 is cleared to 0
during RESET.
DE0: DMA Enable Channel 0 (bit 6).
When DE0 = 1 and
DME = 1, channel 0 DMA is enabled. When a DMA trans-
fer terminates (BCR0 = 0), DE0 is reset to 0 by the DMAC.
When DE0 = 0 and the DMA interrupt is enabled (DIE0 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE0, DWE0 should be writ-
ten with 0 during the same register write access. Writing
DE0 to 0 disables channel 0 DMA. Writing DE0 to 1 en-
ables channel 0 DMA and automatically sets DME (DMA
Main Enable) to 1. DE0 is cleared to 0 during RESET.
DWE1: DE1 Bit Write Enable (bit 5).
When performing
any software write to DE1, DWE1 should be written with 0
during the same access. DWE1 always reads as 1.
DWE0: DE0 Bit Write Enable (bit 4).
When performing
any software write to DE0, DWE0 should be written with 0
during the same access. DWE0 always reads as 1.
DIE1: DMA Interrupt Enable Channel 1 (bit 3).
When
DIE0 is set to 1, the termination channel 1 DMA transfer
(indicated when DE1 = 0) causes a CPU interrupt request
to be generated. When DIE0 = 0, the channel 0 DMA ter-
mination interrupt is disabled. DIE0 is cleared to 0 during
RESET.
DIE0: DMA Interrupt Enable Channel 0 (bit 2).
When
DIE0 is set to 1, the termination channel 0 of DMA transfer
(indicated when DE0=0) causes a CPU interrupt request to
be generated. When DIE0=0, the channel 0 DMA termina-
tion interrupt is disabled. DIE0 is cleared to 0 during RE-
SET.
DME: DMA Main Enable (bit 0).
A DMA operation is only
enabled when its DE bit (DE0 for channel 0, DE1 for chan-
nel 1) and the DME bit is set to 1.
When NMI occurs, DME is reset to 0, thus disabling DMA
activity during the NMI interrupt service routine. To restart
DMA, DE- and/or DE1 should be written with 1 (even if the
contents are already 1). This automatically sets DME to 1,
allowing DMA operations to continue. Note that DME can-
not be directly written. It is cleared to 0 by NMI or indirectly
set to 1 by setting DE0 and/or DE1 to 1. DME is cleared to
0 during RESET.
Figure 72. DMA Status Register (DSTAT: I/O Address = 30H)
Bit
DE1
DE0
DWE1
7
6
5
4
3
2
1
0
R/W
R/W
W
DWE0
DIE1
DIE0
DME
W
R/W
R/W
R
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