參數(shù)資料
型號(hào): Z8S18006PSC
廠商: ZiLOG, Inc.
元件分類(lèi): 微處理器
英文描述: CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE
中文描述: 強(qiáng)化Z180微處理器
文件頁(yè)數(shù): 60/70頁(yè)
文件大?。?/td> 387K
代理商: Z8S18006PSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-60
P R E L I M I N A R Y
DS971800401
Opcode is fetched during the interrupt acknowledge cycle
for INT
0
when Mode 0 is used.
When
Z80180/Z8S180/Z8L180 operates as follows:
a
TRAP
interrupt
occurs,
the
1.
The TRAP bit in the Interrupt TRAP/Control (ITC)
register is set to 1.
2.
The current PC (Program Counter) value, reflecting
the location of the undefined Opcode, is saved on the
stack.
3.
The Z80180/Z8S180/Z8L180 vectors to logical
address 0. Note that if logical address 0000H is
mapped to physical address 00000H, the vector is the
same as for RESET. In this case, testing the TRAP bit
in ITC will reveal whether the restart at physical
address 00000H was caused by RESET or TRAP.
All TRAP interrupts occur after fetching an undefined sec-
ond Opcode byte following one of the “prefix” Opcodes
CBH, DDH, EDH, or FDH, or after fetching an undefined
third Opcode byte following one of the “double prefix” Op-
codes DDCBH or FDCBH.
The state of the Undefined Fetch Object (UFO) bit in ITC
allows TRAP software to correctly “adjust” the stacked PC,
depending on whether the second or third byte of the Op-
code generated the TRAP. If UFO=0, the starting address
of the invalid instruction is equal to the stacked PC-1. If
UFO=1, the starting address of the invalid instruction is
equal to the stacked PC-2.
Figure 76. TRAP Timing-2
nd
Opcode Undefined
T
1
T
2
T
3
T
TP
T
i
T
i
T
i
T
i
T
i
T
1
T
2
T
3
T
2
T
3
T
1
T
1
T
2
A
0
-A
18
(A
19
)
φ
D
0
-D
7
PC
0000H
SP-1
Undefined
Opcode
MREQ
M1
RD
WR
T
3
SP-2
PC
H
PC
L
2nd Opcode
Fetch Cycle
PC Stacking
Opcode
Fetch Cycle
Restart
from 0000H
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